
Nicholas A. Smith
Examiner (ID: 15161, Phone: (571)272-8760 , Office: P/1754 )
| Most Active Art Unit | 1754 |
| Art Unit(s) | 1754, 4145, 1723, 1795, 1794, 1752, 1753, 4100, 1742 |
| Total Applications | 1294 |
| Issued Applications | 796 |
| Pending Applications | 89 |
| Abandoned Applications | 418 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8778783
[patent_doc_number] => 20130100758
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-25
[patent_title] => 'LOCAL WORD LINE DRIVER'
[patent_app_type] => utility
[patent_app_number] => 13/713883
[patent_app_country] => US
[patent_app_date] => 2012-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 6013
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13713883
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/713883 | Local word line driver | Dec 12, 2012 | Issued |
Array
(
[id] => 8864742
[patent_doc_number] => 20130148445
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-06-13
[patent_title] => 'LOCAL WORD LINE DRIVER'
[patent_app_type] => utility
[patent_app_number] => 13/713829
[patent_app_country] => US
[patent_app_date] => 2012-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 6400
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13713829
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/713829 | Local word line driver | Dec 12, 2012 | Issued |
Array
(
[id] => 9833226
[patent_doc_number] => 08942052
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-27
[patent_title] => 'Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages'
[patent_app_type] => utility
[patent_app_number] => 13/682821
[patent_app_country] => US
[patent_app_date] => 2012-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5528
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13682821
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/682821 | Complementary metal-oxide-semiconductor (CMOS) min/max voltage circuit for switching between multiple voltages | Nov 20, 2012 | Issued |
Array
(
[id] => 9461846
[patent_doc_number] => 20140126273
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-05-08
[patent_title] => 'POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/667603
[patent_app_country] => US
[patent_app_date] => 2012-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6614
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13667603
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/667603 | POWER MANAGEMENT SRAM GLOBAL BIT LINE PRECHARGE CIRCUIT | Nov 1, 2012 | Abandoned |
Array
(
[id] => 9033025
[patent_doc_number] => 20130235663
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-12
[patent_title] => 'VOLTAGE MODE SENSING FOR LOW POWER FLASH MEMORY'
[patent_app_type] => utility
[patent_app_number] => 13/665409
[patent_app_country] => US
[patent_app_date] => 2012-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 8670
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13665409
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/665409 | Voltage mode sensing for low power flash memory | Oct 30, 2012 | Issued |
Array
(
[id] => 8778773
[patent_doc_number] => 20130100748
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-25
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/655077
[patent_app_country] => US
[patent_app_date] => 2012-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8572
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655077
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/655077 | Semiconductor memory device and method for driving the same | Oct 17, 2012 | Issued |
Array
(
[id] => 9434154
[patent_doc_number] => 20140112060
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-04-24
[patent_title] => 'SRAM GLOBAL PRECHARGE, DISCHARGE, AND SENSE'
[patent_app_type] => utility
[patent_app_number] => 13/655003
[patent_app_country] => US
[patent_app_date] => 2012-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4791
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655003
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/655003 | SRAM global precharge, discharge, and sense | Oct 17, 2012 | Issued |
Array
(
[id] => 8902810
[patent_doc_number] => 20130170313
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-04
[patent_title] => 'WORDLINE DRIVER'
[patent_app_type] => utility
[patent_app_number] => 13/646497
[patent_app_country] => US
[patent_app_date] => 2012-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8789
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13646497
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/646497 | Wordline driver | Oct 4, 2012 | Issued |
Array
(
[id] => 8731821
[patent_doc_number] => 20130077390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-03-28
[patent_title] => 'MAGNETIC RANDOM ACCESS MEMORY (MRAM) CELL, METHOD FOR WRITING AND READING THE MRAM CELL USING A SELF-REFERENCED READ OPERATION'
[patent_app_type] => utility
[patent_app_number] => 13/622513
[patent_app_country] => US
[patent_app_date] => 2012-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5354
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13622513
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/622513 | MAGNETIC RANDOM ACCESS MEMORY (MRAM) CELL, METHOD FOR WRITING AND READING THE MRAM CELL USING A SELF-REFERENCED READ OPERATION | Sep 18, 2012 | Abandoned |
Array
(
[id] => 10645115
[patent_doc_number] => 09361986
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-07
[patent_title] => 'High endurance non-volatile storage'
[patent_app_type] => utility
[patent_app_number] => 13/622045
[patent_app_country] => US
[patent_app_date] => 2012-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 62
[patent_no_of_words] => 24566
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13622045
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/622045 | High endurance non-volatile storage | Sep 17, 2012 | Issued |
Array
(
[id] => 9368956
[patent_doc_number] => 20140078829
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-20
[patent_title] => 'NON-VOLATILE MEMORY (NVM) WITH ADAPTIVE WRITE OPERATIONS'
[patent_app_type] => utility
[patent_app_number] => 13/616169
[patent_app_country] => US
[patent_app_date] => 2012-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7406
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13616169
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/616169 | Non-volatile memory (NVM) with adaptive write operations | Sep 13, 2012 | Issued |
Array
(
[id] => 9210831
[patent_doc_number] => 20140010008
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-09
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/615951
[patent_app_country] => US
[patent_app_date] => 2012-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9003
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13615951
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/615951 | Semiconductor memory device and method of operating the same | Sep 13, 2012 | Issued |
Array
(
[id] => 10531045
[patent_doc_number] => 09257185
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-09
[patent_title] => 'Nonvolatile memory device, nonvolatile memory system, program method thereof, and operation method of controller controlling the same'
[patent_app_type] => utility
[patent_app_number] => 13/618605
[patent_app_country] => US
[patent_app_date] => 2012-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 24
[patent_no_of_words] => 14510
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13618605
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/618605 | Nonvolatile memory device, nonvolatile memory system, program method thereof, and operation method of controller controlling the same | Sep 13, 2012 | Issued |
Array
(
[id] => 9119799
[patent_doc_number] => 20130286721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-31
[patent_title] => 'LOW SENSING CURRENT NON-VOLATILE FLIP-FLOP'
[patent_app_type] => utility
[patent_app_number] => 13/613205
[patent_app_country] => US
[patent_app_date] => 2012-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5222
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13613205
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/613205 | Low sensing current non-volatile flip-flop | Sep 12, 2012 | Issued |
Array
(
[id] => 9361910
[patent_doc_number] => 20140071783
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-13
[patent_title] => 'MEMORY DEVICE WITH CLOCK GENERATION BASED ON SEGMENTED ADDRESS CHANGE DETECTION'
[patent_app_type] => utility
[patent_app_number] => 13/613981
[patent_app_country] => US
[patent_app_date] => 2012-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6391
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13613981
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/613981 | MEMORY DEVICE WITH CLOCK GENERATION BASED ON SEGMENTED ADDRESS CHANGE DETECTION | Sep 12, 2012 | Abandoned |
Array
(
[id] => 9361906
[patent_doc_number] => 20140071779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-13
[patent_title] => 'E-FUSE ARRAY CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 13/610451
[patent_app_country] => US
[patent_app_date] => 2012-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2769
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610451
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/610451 | E-fuse array circuit | Sep 10, 2012 | Issued |
Array
(
[id] => 8926757
[patent_doc_number] => 20130182517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-18
[patent_title] => 'FAIL ADDRESS STORAGE CIRCUIT, REDUNDANCY CONTROL CIRCUIT, METHOD FOR STORING FAIL ADDRESS AND METHOD FOR CONTROLLING REDUNDANCY'
[patent_app_type] => utility
[patent_app_number] => 13/610283
[patent_app_country] => US
[patent_app_date] => 2012-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8585
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13610283
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/610283 | Fail address storage circuit, redundancy control circuit, method for storing fail address and method for controlling redundancy | Sep 10, 2012 | Issued |
Array
(
[id] => 8584642
[patent_doc_number] => 20130003463
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-01-03
[patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/608587
[patent_app_country] => US
[patent_app_date] => 2012-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4787
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13608587
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/608587 | Nonvolatile semiconductor memory device | Sep 9, 2012 | Issued |
Array
(
[id] => 9052988
[patent_doc_number] => 20130250702
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-09-26
[patent_title] => 'SEMICONDUCTOR MEMORY AND VOLTAGE OUTPUT MEASURING METHOD OF THE SEMICONDUCTOR MEMORY'
[patent_app_type] => utility
[patent_app_number] => 13/607493
[patent_app_country] => US
[patent_app_date] => 2012-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10473
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13607493
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/607493 | Semiconductor memory and voltage output measuring method of the semiconductor memory | Sep 6, 2012 | Issued |
Array
(
[id] => 9010911
[patent_doc_number] => 08526222
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-03
[patent_title] => 'Magnetic random access memory'
[patent_app_type] => utility
[patent_app_number] => 13/606737
[patent_app_country] => US
[patent_app_date] => 2012-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 24
[patent_no_of_words] => 7752
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13606737
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/606737 | Magnetic random access memory | Sep 6, 2012 | Issued |