
Nicholas Ieva
Examiner (ID: 15104)
| Most Active Art Unit | 2836 |
| Art Unit(s) | 2836 |
| Total Applications | 229 |
| Issued Applications | 124 |
| Pending Applications | 4 |
| Abandoned Applications | 102 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18105507
[patent_doc_number] => 11545404
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-03
[patent_title] => III-V compound semiconductor dies with stress-treated inactive surfaces to avoid packaging-induced fractures, and related methods
[patent_app_type] => utility
[patent_app_number] => 16/868147
[patent_app_country] => US
[patent_app_date] => 2020-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 18
[patent_no_of_words] => 9012
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868147
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/868147 | III-V compound semiconductor dies with stress-treated inactive surfaces to avoid packaging-induced fractures, and related methods | May 5, 2020 | Issued |
Array
(
[id] => 16677503
[patent_doc_number] => 20210066269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-04
[patent_title] => SEMICONDCUTOR PACKAGES
[patent_app_type] => utility
[patent_app_number] => 16/866561
[patent_app_country] => US
[patent_app_date] => 2020-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7518
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16866561
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/866561 | Semiconductor packages | May 4, 2020 | Issued |
Array
(
[id] => 17493460
[patent_doc_number] => 11282774
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-22
[patent_title] => Power semiconductor module arrangement
[patent_app_type] => utility
[patent_app_number] => 16/867074
[patent_app_country] => US
[patent_app_date] => 2020-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 4027
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 227
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16867074
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/867074 | Power semiconductor module arrangement | May 4, 2020 | Issued |
Array
(
[id] => 17152495
[patent_doc_number] => 11145586
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-12
[patent_title] => Interposer and electronic device
[patent_app_type] => utility
[patent_app_number] => 16/861731
[patent_app_country] => US
[patent_app_date] => 2020-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 14730
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861731
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/861731 | Interposer and electronic device | Apr 28, 2020 | Issued |
Array
(
[id] => 16241769
[patent_doc_number] => 20200259003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => METHOD OF MAKING SEMICONDUCTOR DEVICE COMPRISING FLASH MEMORY AND RESULTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/861668
[patent_app_country] => US
[patent_app_date] => 2020-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5159
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861668
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/861668 | Method of making semiconductor device comprising flash memory and resulting device | Apr 28, 2020 | Issued |
Array
(
[id] => 17122057
[patent_doc_number] => 11133198
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-09-28
[patent_title] => Method of manufacturing packaged device chip
[patent_app_type] => utility
[patent_app_number] => 16/854149
[patent_app_country] => US
[patent_app_date] => 2020-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 6459
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16854149
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/854149 | Method of manufacturing packaged device chip | Apr 20, 2020 | Issued |
Array
(
[id] => 16981554
[patent_doc_number] => 20210225791
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/843876
[patent_app_country] => US
[patent_app_date] => 2020-04-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6460
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16843876
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/843876 | Package structure and method of fabricating the same | Apr 7, 2020 | Issued |
Array
(
[id] => 16707775
[patent_doc_number] => 10957719
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-23
[patent_title] => Semiconductor device and a method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/842315
[patent_app_country] => US
[patent_app_date] => 2020-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 22
[patent_no_of_words] => 7950
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16842315
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/842315 | Semiconductor device and a method of manufacturing the same | Apr 6, 2020 | Issued |
Array
(
[id] => 18040541
[patent_doc_number] => 20220384758
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => Quantum Dot Light-Emitting Device, Manufacturing Method and Display Device
[patent_app_type] => utility
[patent_app_number] => 16/982063
[patent_app_country] => US
[patent_app_date] => 2020-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6744
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16982063
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/982063 | Quantum dot light-emitting device, manufacturing method and display device | Mar 29, 2020 | Issued |
Array
(
[id] => 17224696
[patent_doc_number] => 11177206
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-16
[patent_title] => Double-sided flexible circuit board and layout structure thereof
[patent_app_type] => utility
[patent_app_number] => 16/833826
[patent_app_country] => US
[patent_app_date] => 2020-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1934
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833826
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/833826 | Double-sided flexible circuit board and layout structure thereof | Mar 29, 2020 | Issued |
Array
(
[id] => 17130409
[patent_doc_number] => 20210305178
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-30
[patent_title] => HIGH VOLTAGE ISOLATION BARRIER WITH ELECTRIC OVERSTRESS INTEGRITY
[patent_app_type] => utility
[patent_app_number] => 16/833268
[patent_app_country] => US
[patent_app_date] => 2020-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9201
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833268
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/833268 | High voltage isolation barrier with electric overstress integrity | Mar 26, 2020 | Issued |
Array
(
[id] => 17700212
[patent_doc_number] => 11373946
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-06-28
[patent_title] => Semiconductor package and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 16/830284
[patent_app_country] => US
[patent_app_date] => 2020-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 24
[patent_no_of_words] => 6753
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830284
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/830284 | Semiconductor package and manufacturing method thereof | Mar 25, 2020 | Issued |
Array
(
[id] => 16684316
[patent_doc_number] => 10943807
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-09
[patent_title] => Method and device for alignment of substrates
[patent_app_type] => utility
[patent_app_number] => 16/830389
[patent_app_country] => US
[patent_app_date] => 2020-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 9322
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16830389
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/830389 | Method and device for alignment of substrates | Mar 25, 2020 | Issued |
Array
(
[id] => 17878711
[patent_doc_number] => 11450736
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-20
[patent_title] => Source/drain regions in integrated circuit structures
[patent_app_type] => utility
[patent_app_number] => 16/829357
[patent_app_country] => US
[patent_app_date] => 2020-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 88
[patent_figures_cnt] => 177
[patent_no_of_words] => 14700
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829357
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/829357 | Source/drain regions in integrated circuit structures | Mar 24, 2020 | Issued |
Array
(
[id] => 16759988
[patent_doc_number] => 10978546
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-13
[patent_title] => Display device
[patent_app_type] => utility
[patent_app_number] => 16/824485
[patent_app_country] => US
[patent_app_date] => 2020-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 9102
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16824485
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/824485 | Display device | Mar 18, 2020 | Issued |
Array
(
[id] => 17745664
[patent_doc_number] => 11393746
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Reinforcing package using reinforcing patches
[patent_app_type] => utility
[patent_app_number] => 16/823995
[patent_app_country] => US
[patent_app_date] => 2020-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 30
[patent_no_of_words] => 6830
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823995
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/823995 | Reinforcing package using reinforcing patches | Mar 18, 2020 | Issued |
Array
(
[id] => 16528969
[patent_doc_number] => 20200403050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-24
[patent_title] => DISPLAY PANEL
[patent_app_type] => utility
[patent_app_number] => 16/823224
[patent_app_country] => US
[patent_app_date] => 2020-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16654
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16823224
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/823224 | Display panel | Mar 17, 2020 | Issued |
Array
(
[id] => 16865877
[patent_doc_number] => 11024630
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry
[patent_app_type] => utility
[patent_app_number] => 16/821746
[patent_app_country] => US
[patent_app_date] => 2020-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 24
[patent_no_of_words] => 6182
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821746
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/821746 | Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry | Mar 16, 2020 | Issued |
Array
(
[id] => 17438963
[patent_doc_number] => 11264304
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-01
[patent_title] => Semiconductor structure and associated method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/821922
[patent_app_country] => US
[patent_app_date] => 2020-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3603
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16821922
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/821922 | Semiconductor structure and associated method for manufacturing the same | Mar 16, 2020 | Issued |
Array
(
[id] => 17395885
[patent_doc_number] => 11244909
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-08
[patent_title] => Package structure and method for manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/817407
[patent_app_country] => US
[patent_app_date] => 2020-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 9577
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16817407
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/817407 | Package structure and method for manufacturing the same | Mar 11, 2020 | Issued |