Search

Nicole Erin Kinsey White

Examiner (ID: 11555, Phone: (571)272-9943 , Office: P/1648 )

Most Active Art Unit
1648
Art Unit(s)
1648, 1672, 1671
Total Applications
1138
Issued Applications
564
Pending Applications
130
Abandoned Applications
476

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16486193 [patent_doc_number] => 20200379798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => APPARATUS FOR TRANSMITTING PACKETS USING TIMER INTERRUPT SERVICE ROUTINE [patent_app_type] => utility [patent_app_number] => 16/782968 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16782968 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/782968
APPARATUS FOR TRANSMITTING PACKETS USING TIMER INTERRUPT SERVICE ROUTINE Feb 4, 2020 Abandoned
Array ( [id] => 17469228 [patent_doc_number] => 11275705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Rack switch coupling system [patent_app_type] => utility [patent_app_number] => 16/774872 [patent_app_country] => US [patent_app_date] => 2020-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16774872 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/774872
Rack switch coupling system Jan 27, 2020 Issued
Array ( [id] => 18136237 [patent_doc_number] => 11561916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Processing task deployment in adapter devices and accelerators [patent_app_type] => utility [patent_app_number] => 16/741684 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741684 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741684
Processing task deployment in adapter devices and accelerators Jan 12, 2020 Issued
Array ( [id] => 18826457 [patent_doc_number] => 11841733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Method and system for realizing FPGA server [patent_app_type] => utility [patent_app_number] => 17/791511 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4870 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17791511 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/791511
Method and system for realizing FPGA server Jan 7, 2020 Issued
Array ( [id] => 16255617 [patent_doc_number] => 20200264991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => TRACE LENGTH ON PRINTED CIRCUIT BOARD (PCB) BASED ON INPUT/OUTPUT (I/O) OPERATING SPEED [patent_app_type] => utility [patent_app_number] => 16/736542 [patent_app_country] => US [patent_app_date] => 2020-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736542 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/736542
Trace length on printed circuit board (PCB) based on input/output (I/O) operating speed Jan 6, 2020 Issued
Array ( [id] => 16431605 [patent_doc_number] => 10831687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Aligning received bad data indicators (BDIs) with received data on a cross-chip link [patent_app_type] => utility [patent_app_number] => 16/736019 [patent_app_country] => US [patent_app_date] => 2020-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6635 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736019 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/736019
Aligning received bad data indicators (BDIs) with received data on a cross-chip link Jan 6, 2020 Issued
Array ( [id] => 16164115 [patent_doc_number] => 20200220290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => ELECTRONIC DEVICE AND HOST THEREOF [patent_app_type] => utility [patent_app_number] => 16/735142 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735142
ELECTRONIC DEVICE AND HOST THEREOF Jan 5, 2020 Abandoned
Array ( [id] => 16810516 [patent_doc_number] => 20210133071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => SIGNAL TUNING METHOD FOR PERIPHERAL COMPONENT INTERCONNECT EXPRESS AND COMPUTER SYSTEM USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/732363 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732363 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732363
Signal tuning method for peripheral component interconnect express and computer system using the same Jan 1, 2020 Issued
Array ( [id] => 17557977 [patent_doc_number] => 11314682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Switchable I2S interface [patent_app_type] => utility [patent_app_number] => 16/729044 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3068 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729044 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/729044
Switchable I2S interface Dec 26, 2019 Issued
Array ( [id] => 15870891 [patent_doc_number] => 20200142849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => NAND SWITCH [patent_app_type] => utility [patent_app_number] => 16/726763 [patent_app_country] => US [patent_app_date] => 2019-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16726763 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/726763
NAND switch Dec 23, 2019 Issued
Array ( [id] => 16780278 [patent_doc_number] => 20210117357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => VIRTUAL MULTICHANNEL STORAGE CONTROL [patent_app_type] => utility [patent_app_number] => 16/658269 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7516 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658269 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658269
VIRTUAL MULTICHANNEL STORAGE CONTROL Oct 20, 2019 Abandoned
Array ( [id] => 15804765 [patent_doc_number] => 20200125525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => NONVOLATILE LOGIC MEMORY FOR COMPUTING MODULE RECONFIGURATION [patent_app_type] => utility [patent_app_number] => 16/658928 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658928 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658928
Nonvolatile logic memory for computing module reconfiguration Oct 20, 2019 Issued
Array ( [id] => 15804755 [patent_doc_number] => 20200125520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => Methods and Systems for Assigning Addresses to Devices That Use Master / Slave Communication Protocols [patent_app_type] => utility [patent_app_number] => 16/591343 [patent_app_country] => US [patent_app_date] => 2019-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16591343 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/591343
Methods and Systems for Assigning Addresses to Devices That Use Master / Slave Communication Protocols Oct 1, 2019 Abandoned
Array ( [id] => 16426151 [patent_doc_number] => 20200351349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => SYSTEM AND METHOD FOR COMMUNICATION BETWEEN BMSs [patent_app_type] => utility [patent_app_number] => 16/763075 [patent_app_country] => US [patent_app_date] => 2019-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16763075 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/763075
System and method for communication between BMSs Sep 24, 2019 Issued
Array ( [id] => 15622913 [patent_doc_number] => 20200081861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => HIGH SPEED INTERFACE CONNECTION APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 16/568505 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16568505 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/568505
HIGH SPEED INTERFACE CONNECTION APPARATUS AND METHOD Sep 11, 2019 Abandoned
Array ( [id] => 15594611 [patent_doc_number] => 20200073840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => DYNAMICALLY CHANGING CONFIGURATION OF DATA PROCESSING UNIT WHEN CONNECTED TO STORAGE DEVICE OR COMPUTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/560948 [patent_app_country] => US [patent_app_date] => 2019-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16560948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/560948
Dynamically changing configuration of data processing unit when connected to storage device or computing device Sep 3, 2019 Issued
Array ( [id] => 17802134 [patent_doc_number] => 11416435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Flexible datapath offload chaining [patent_app_type] => utility [patent_app_number] => 16/559381 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559381 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559381
Flexible datapath offload chaining Sep 2, 2019 Issued
Array ( [id] => 15271997 [patent_doc_number] => 20190384733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => Enabling Sync Header Suppression Latency Optimization In The Presence Of Retimers For Serial Interconnect [patent_app_type] => utility [patent_app_number] => 16/554974 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554974 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/554974
Enabling sync header suppression latency optimization in the presence of retimers for serial interconnect Aug 28, 2019 Issued
Array ( [id] => 15271995 [patent_doc_number] => 20190384732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => METHOD, APPARATUS AND SYSTEM FOR CHANGING TO WHICH REMOTE DEVICE A LOCAL DEVICE IS IN COMMUNICATION VIA A COMMUNICATION MEDIUM THROUGH USE OF INTERRUPTION OF THE COMMUNICATION MEDIUM [patent_app_type] => utility [patent_app_number] => 16/554787 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554787 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/554787
Method, apparatus and system for changing to which remote device a local device is in communication via a communication medium through use of interruption of the communication medium Aug 28, 2019 Issued
Array ( [id] => 16623602 [patent_doc_number] => 20210042255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => Methods for Using High-Speed Data Communication Fabric to Enable Cross-System Command Buffer Writing for Data Retrieval in Cloud Gaming [patent_app_type] => utility [patent_app_number] => 16/556046 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556046 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/556046
Methods for Using High-Speed Data Communication Fabric to Enable Cross-System Command Buffer Writing for Data Retrieval in Cloud Gaming Aug 28, 2019 Abandoned
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