Search

Nicole Erin Kinsey White

Examiner (ID: 11555, Phone: (571)272-9943 , Office: P/1648 )

Most Active Art Unit
1648
Art Unit(s)
1648, 1672, 1671
Total Applications
1138
Issued Applications
564
Pending Applications
130
Abandoned Applications
476

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19581251 [patent_doc_number] => 12147364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Auxiliary processor and electronic system comprising the same [patent_app_type] => utility [patent_app_number] => 17/748403 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 9008 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748403
Auxiliary processor and electronic system comprising the same May 18, 2022 Issued
Array ( [id] => 19092606 [patent_doc_number] => 11954055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Mapping high-speed, point-to-point interface channels to packet virtual channels [patent_app_type] => utility [patent_app_number] => 17/744085 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 14050 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744085 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744085
Mapping high-speed, point-to-point interface channels to packet virtual channels May 12, 2022 Issued
Array ( [id] => 17812219 [patent_doc_number] => 20220264054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => DEVICE IDENTIFICATION AND POWER STATE DETERMINATION USING MEDIA DEVICE INFORMATION [patent_app_type] => utility [patent_app_number] => 17/736401 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/736401
Device identification and power state determination using media device information May 3, 2022 Issued
Array ( [id] => 19347514 [patent_doc_number] => 20240256477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => METHOD AND APPARATUS FOR PROCESSING DMA, AND COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/564515 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18564515 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/564515
METHOD AND APPARATUS FOR PROCESSING DMA, AND COMPUTER-READABLE STORAGE MEDIUM Apr 28, 2022 Pending
Array ( [id] => 17794302 [patent_doc_number] => 20220253394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => RACK ASSEMBLY PROVIDING HIGH SPEED STORAGE ACCESS FOR COMPUTE NODES TO A STORAGE SERVER THROUGH A PCI EXPRESS FABRIC [patent_app_type] => utility [patent_app_number] => 17/731151 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731151
Rack assembly providing high speed storage access for compute nodes to a storage server through a PCI express fabric Apr 26, 2022 Issued
Array ( [id] => 19340356 [patent_doc_number] => 12050544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Predicting free buffer space in a USB extension environment [patent_app_type] => utility [patent_app_number] => 17/713072 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17713072 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/713072
Predicting free buffer space in a USB extension environment Apr 3, 2022 Issued
Array ( [id] => 17706957 [patent_doc_number] => 20220206963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => ELECTRONIC TOOL AND METHODS WITH AUDIO FOR MEETINGS [patent_app_type] => utility [patent_app_number] => 17/698860 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698860 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/698860
ELECTRONIC TOOL AND METHODS WITH AUDIO FOR MEETINGS Mar 17, 2022 Abandoned
Array ( [id] => 17629291 [patent_doc_number] => 20220164306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => Direct Network Access by a Memory Mapped Peripheral Device for Scheduled Data Transfer on the Network [patent_app_type] => utility [patent_app_number] => 17/669708 [patent_app_country] => US [patent_app_date] => 2022-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11146 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669708 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669708
Direct network access by a memory mapped peripheral device for scheduled data transfer on the network Feb 10, 2022 Issued
Array ( [id] => 19917476 [patent_doc_number] => 12292845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Methods and systems for establishing direct communications between a server computer and a smart network interface controller [patent_app_type] => utility [patent_app_number] => 17/669272 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669272 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669272
Methods and systems for establishing direct communications between a server computer and a smart network interface controller Feb 9, 2022 Issued
Array ( [id] => 19084895 [patent_doc_number] => 20240111696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => METHOD FOR INTEGRATING INTO A DATA TRANSMISSION A NUMBER OF I/O MODULES CONNECTED TO AN I/O STATION, STATION HEAD FOR CARRYING OUT A METHOD OF THIS TYPE, AND SYSTEM HAVING A STATION HEAD OF THIS TYPE [patent_app_type] => utility [patent_app_number] => 18/276333 [patent_app_country] => US [patent_app_date] => 2022-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18276333 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/276333
METHOD FOR INTEGRATING INTO A DATA TRANSMISSION A NUMBER OF I/O MODULES CONNECTED TO AN I/O STATION, STATION HEAD FOR CARRYING OUT A METHOD OF THIS TYPE, AND SYSTEM HAVING A STATION HEAD OF THIS TYPE Feb 6, 2022 Pending
Array ( [id] => 17794308 [patent_doc_number] => 20220253400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => SYSTEM ON CHIP AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/591260 [patent_app_country] => US [patent_app_date] => 2022-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5273 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/591260
SYSTEM ON CHIP AND CONTROL METHOD Feb 1, 2022 Abandoned
Array ( [id] => 19167227 [patent_doc_number] => 11983132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => USB connector functionality modification system [patent_app_type] => utility [patent_app_number] => 17/583409 [patent_app_country] => US [patent_app_date] => 2022-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17583409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/583409
USB connector functionality modification system Jan 24, 2022 Issued
Array ( [id] => 17763524 [patent_doc_number] => 20220237136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => SWITCHING METHOD OF USB SWITCH ELEMENT FOR IN-VEHICLE HOST SYSTEM [patent_app_type] => utility [patent_app_number] => 17/578506 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2671 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578506
Switching method of USB switch element for in-vehicle host system Jan 18, 2022 Issued
Array ( [id] => 17751588 [patent_doc_number] => 20220229793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => METHOD AND SYSTEM OF LOW PIN COUNT (LPC) BUS SERIAL INTERRUPT [patent_app_type] => utility [patent_app_number] => 17/575340 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575340
Method and system of low pin count (LPC) bus serial interrupt Jan 12, 2022 Issued
Array ( [id] => 18501427 [patent_doc_number] => 20230224261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => NETWORK INTERFACE DEVICE [patent_app_type] => utility [patent_app_number] => 17/571292 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571292 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571292
NETWORK INTERFACE DEVICE Jan 6, 2022 Pending
Array ( [id] => 17550266 [patent_doc_number] => 20220121608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => NONVOLATILE LOGIC MEMORY FOR COMPUTING MODULE RECONFIGURATION [patent_app_type] => utility [patent_app_number] => 17/564487 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564487 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564487
Nonvolatile logic memory for computing module reconfiguration Dec 28, 2021 Issued
Array ( [id] => 17722258 [patent_doc_number] => 20220214980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => OPTICAL TRANSCEIVER AND OPTICAL TRANSCEIVER CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/646025 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646025 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646025
OPTICAL TRANSCEIVER AND OPTICAL TRANSCEIVER CONTROL METHOD Dec 26, 2021 Abandoned
Array ( [id] => 17535519 [patent_doc_number] => 20220114128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => Enabling Sync Header Suppression Latency Optimization In The Presence Of Retimers For Serial Interconnect [patent_app_type] => utility [patent_app_number] => 17/559002 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559002 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559002
Enabling sync header suppression latency optimization in the presence of retimers for serial interconnect Dec 21, 2021 Issued
Array ( [id] => 18393509 [patent_doc_number] => 20230161729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => Detection System for PCIe CEM Connection Interface of Circuit Board and Method Thereof [patent_app_type] => utility [patent_app_number] => 17/554307 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 465 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/554307
Detection System for PCIe CEM Connection Interface of Circuit Board and Method Thereof Dec 16, 2021 Abandoned
Array ( [id] => 17659346 [patent_doc_number] => 20220179811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => DYNAMIC DMA BUFFER MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/547077 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547077 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547077
DYNAMIC DMA BUFFER MANAGEMENT Dec 8, 2021 Abandoned
Menu