
Nicole M. Barreca
Examiner (ID: 14576)
| Most Active Art Unit | 1756 |
| Art Unit(s) | 1756 |
| Total Applications | 389 |
| Issued Applications | 279 |
| Pending Applications | 40 |
| Abandoned Applications | 70 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 749098
[patent_doc_number] => 07022440
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-04
[patent_title] => 'Resist pattern defined by inwardly arched lines'
[patent_app_type] => utility
[patent_app_number] => 10/938567
[patent_app_country] => US
[patent_app_date] => 2004-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 5586
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/022/07022440.pdf
[firstpage_image] =>[orig_patent_app_number] => 10938567
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/938567 | Resist pattern defined by inwardly arched lines | Sep 12, 2004 | Issued |
Array
(
[id] => 7202001
[patent_doc_number] => 20050042549
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-24
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/937366
[patent_app_country] => US
[patent_app_date] => 2004-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4124
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0042/20050042549.pdf
[firstpage_image] =>[orig_patent_app_number] => 10937366
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/937366 | Semiconductor device and manufacturing method thereof | Sep 9, 2004 | Issued |
Array
(
[id] => 5903063
[patent_doc_number] => 20060046202
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'INTEGRAL PLATED RESISTOR AND METHOD FOR THE MANUFACTURE OF PRINTED CIRCUIT BOARDS COMPRISING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 10/925589
[patent_app_country] => US
[patent_app_date] => 2004-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2786
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0046/20060046202.pdf
[firstpage_image] =>[orig_patent_app_number] => 10925589
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/925589 | Integral plated resistor and method for the manufacture of printed circuit boards comprising the same | Aug 24, 2004 | Issued |
Array
(
[id] => 7127170
[patent_doc_number] => 20050058914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-17
[patent_title] => 'Pattern designing method, photomask manufacturing method, resist pattern forming method and semiconductor device manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 10/912228
[patent_app_country] => US
[patent_app_date] => 2004-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3354
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0058/20050058914.pdf
[firstpage_image] =>[orig_patent_app_number] => 10912228
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/912228 | Pattern designing method, photomask manufacturing method, resist pattern forming method and semiconductor device manufacturing method | Aug 5, 2004 | Abandoned |
Array
(
[id] => 777105
[patent_doc_number] => 06998224
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-02-14
[patent_title] => 'Plasma deposited optical waveguide'
[patent_app_type] => utility
[patent_app_number] => 10/899231
[patent_app_country] => US
[patent_app_date] => 2004-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 17
[patent_no_of_words] => 8302
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/998/06998224.pdf
[firstpage_image] =>[orig_patent_app_number] => 10899231
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/899231 | Plasma deposited optical waveguide | Jul 25, 2004 | Issued |
Array
(
[id] => 698277
[patent_doc_number] => 07067237
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-27
[patent_title] => 'Method for forming pattern of one-dimensional nanostructure'
[patent_app_type] => utility
[patent_app_number] => 10/876623
[patent_app_country] => US
[patent_app_date] => 2004-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3630
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/067/07067237.pdf
[firstpage_image] =>[orig_patent_app_number] => 10876623
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/876623 | Method for forming pattern of one-dimensional nanostructure | Jun 27, 2004 | Issued |
Array
(
[id] => 7458585
[patent_doc_number] => 20040197488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'Plasma deposited selective wetting material'
[patent_app_type] => new
[patent_app_number] => 10/831442
[patent_app_country] => US
[patent_app_date] => 2004-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7960
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20040197488.pdf
[firstpage_image] =>[orig_patent_app_number] => 10831442
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/831442 | Plasma deposited selective wetting material | Apr 23, 2004 | Issued |
Array
(
[id] => 7337544
[patent_doc_number] => 20040245213
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'Process for making circuit board or lead frame'
[patent_app_type] => new
[patent_app_number] => 10/822825
[patent_app_country] => US
[patent_app_date] => 2004-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 9113
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0245/20040245213.pdf
[firstpage_image] =>[orig_patent_app_number] => 10822825
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/822825 | Process for making circuit board or lead frame | Apr 12, 2004 | Issued |
Array
(
[id] => 7083037
[patent_doc_number] => 20050048417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Technique for enhancing accuracy of critical dimensions of a gate electrode by using characteristics of an ARC layer'
[patent_app_type] => utility
[patent_app_number] => 10/813374
[patent_app_country] => US
[patent_app_date] => 2004-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5410
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20050048417.pdf
[firstpage_image] =>[orig_patent_app_number] => 10813374
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/813374 | Technique for enhancing accuracy of critical dimensions of a gate electrode by using characteristics of an ARC layer | Mar 29, 2004 | Issued |
Array
(
[id] => 7060947
[patent_doc_number] => 20050003308
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Method for fabricating a contact hole plane in a memory module'
[patent_app_type] => utility
[patent_app_number] => 10/811509
[patent_app_country] => US
[patent_app_date] => 2004-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6999
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0003/20050003308.pdf
[firstpage_image] =>[orig_patent_app_number] => 10811509
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/811509 | Method for fabricating a contact hole plane in a memory module | Mar 28, 2004 | Issued |
Array
(
[id] => 671958
[patent_doc_number] => 07090966
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-15
[patent_title] => 'Process of surface treatment, surface treating device, surface treated plate, and electro-optic device, and electronic equipment'
[patent_app_type] => utility
[patent_app_number] => 10/809201
[patent_app_country] => US
[patent_app_date] => 2004-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 9729
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/090/07090966.pdf
[firstpage_image] =>[orig_patent_app_number] => 10809201
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/809201 | Process of surface treatment, surface treating device, surface treated plate, and electro-optic device, and electronic equipment | Mar 24, 2004 | Issued |
Array
(
[id] => 765813
[patent_doc_number] => 07008737
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-07
[patent_title] => 'Gray scale x-ray mask'
[patent_app_type] => utility
[patent_app_number] => 10/804771
[patent_app_country] => US
[patent_app_date] => 2004-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 4588
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/008/07008737.pdf
[firstpage_image] =>[orig_patent_app_number] => 10804771
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/804771 | Gray scale x-ray mask | Mar 18, 2004 | Issued |
Array
(
[id] => 7404537
[patent_doc_number] => 20040175658
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Embossing tool having an arbitrary three-dimensional microstructure'
[patent_app_type] => new
[patent_app_number] => 10/804798
[patent_app_country] => US
[patent_app_date] => 2004-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4579
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0175/20040175658.pdf
[firstpage_image] =>[orig_patent_app_number] => 10804798
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/804798 | Embossing tool having an arbitrary three-dimensional microstructure | Mar 18, 2004 | Abandoned |
Array
(
[id] => 7427434
[patent_doc_number] => 20040161703
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-19
[patent_title] => 'Substrate having fine lines, method for manufacturing the same, electron-source substrate, and image display apparatus'
[patent_app_type] => new
[patent_app_number] => 10/781790
[patent_app_country] => US
[patent_app_date] => 2004-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 9907
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 17
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0161/20040161703.pdf
[firstpage_image] =>[orig_patent_app_number] => 10781790
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/781790 | Substrate having fine lines, method for manufacturing the same, electron-source substrate, and image display apparatus | Feb 19, 2004 | Issued |
Array
(
[id] => 740485
[patent_doc_number] => 07029821
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-18
[patent_title] => 'Photoresist and organic antireflective coating compositions'
[patent_app_type] => utility
[patent_app_number] => 10/777997
[patent_app_country] => US
[patent_app_date] => 2004-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4959
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/029/07029821.pdf
[firstpage_image] =>[orig_patent_app_number] => 10777997
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/777997 | Photoresist and organic antireflective coating compositions | Feb 10, 2004 | Issued |
Array
(
[id] => 7286492
[patent_doc_number] => 20040146790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-29
[patent_title] => 'Method of increasing the shelf life of a blank photomask substrate'
[patent_app_type] => new
[patent_app_number] => 10/758827
[patent_app_country] => US
[patent_app_date] => 2004-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 11828
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20040146790.pdf
[firstpage_image] =>[orig_patent_app_number] => 10758827
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/758827 | Method of increasing the shelf life of a blank photomask substrate | Jan 14, 2004 | Issued |
Array
(
[id] => 7262433
[patent_doc_number] => 20040241422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-02
[patent_title] => 'Conductor track structures and method for production thereof'
[patent_app_type] => new
[patent_app_number] => 10/751111
[patent_app_country] => US
[patent_app_date] => 2004-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2091
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0241/20040241422.pdf
[firstpage_image] =>[orig_patent_app_number] => 10751111
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/751111 | Conductor track structures and method for production thereof | Jan 4, 2004 | Issued |
Array
(
[id] => 710057
[patent_doc_number] => 07056648
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-06
[patent_title] => 'Method for isotropic etching of copper'
[patent_app_type] => utility
[patent_app_number] => 10/664017
[patent_app_country] => US
[patent_app_date] => 2003-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4139
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/056/07056648.pdf
[firstpage_image] =>[orig_patent_app_number] => 10664017
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/664017 | Method for isotropic etching of copper | Sep 16, 2003 | Issued |
Array
(
[id] => 7286541
[patent_doc_number] => 20040146811
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-29
[patent_title] => 'Method of preparing patterned colloidal crystals'
[patent_app_type] => new
[patent_app_number] => 10/662088
[patent_app_country] => US
[patent_app_date] => 2003-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4060
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0146/20040146811.pdf
[firstpage_image] =>[orig_patent_app_number] => 10662088
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/662088 | Method of preparing patterned colloidal crystals | Sep 11, 2003 | Issued |
Array
(
[id] => 675514
[patent_doc_number] => 07087363
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-08
[patent_title] => 'Method of forming a top gate thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 10/650977
[patent_app_country] => US
[patent_app_date] => 2003-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 28
[patent_no_of_words] => 3946
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/087/07087363.pdf
[firstpage_image] =>[orig_patent_app_number] => 10650977
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/650977 | Method of forming a top gate thin film transistor | Aug 28, 2003 | Issued |