Search

Nilufa Rahim

Examiner (ID: 1665, Phone: (571)272-8926 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893, RD00
Total Applications
618
Issued Applications
451
Pending Applications
99
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16835148 [patent_doc_number] => 11011407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Wafer processing method using a ring frame and a polyolefin sheet [patent_app_type] => utility [patent_app_number] => 16/696204 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8197 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696204 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696204
Wafer processing method using a ring frame and a polyolefin sheet Nov 25, 2019 Issued
Array ( [id] => 16192011 [patent_doc_number] => 20200232860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => MEMS PRESSURE SENSOR [patent_app_type] => utility [patent_app_number] => 16/694607 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694607 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/694607
MEMS pressure sensor Nov 24, 2019 Issued
Array ( [id] => 15625213 [patent_doc_number] => 20200083011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => ELECTRICALLY CONTROLLABLE INTEGRATED SWITCH [patent_app_type] => utility [patent_app_number] => 16/680940 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680940 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/680940
Electrically controllable integrated switch Nov 11, 2019 Issued
Array ( [id] => 15597741 [patent_doc_number] => 20200075405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => Etching to Reduce Line Wiggling [patent_app_type] => utility [patent_app_number] => 16/679940 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10616 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679940 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679940
Etching to reduce line wiggling Nov 10, 2019 Issued
Array ( [id] => 17590765 [patent_doc_number] => 11329042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof [patent_app_type] => utility [patent_app_number] => 16/678695 [patent_app_country] => US [patent_app_date] => 2019-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 45 [patent_no_of_words] => 15881 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16678695 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/678695
Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof Nov 7, 2019 Issued
Array ( [id] => 16828029 [patent_doc_number] => 20210143322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => Etching and Encapsulation Scheme for Magnetic Tunnel Junction Fabrication [patent_app_type] => utility [patent_app_number] => 16/677053 [patent_app_country] => US [patent_app_date] => 2019-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16677053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/677053
Etching and encapsulation scheme for magnetic tunnel junction fabrication Nov 6, 2019 Issued
Array ( [id] => 16881077 [patent_doc_number] => 11031234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Wafer processing method including applying a polyolefin sheet to a wafer [patent_app_type] => utility [patent_app_number] => 16/674276 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8139 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/674276
Wafer processing method including applying a polyolefin sheet to a wafer Nov 4, 2019 Issued
Array ( [id] => 15873289 [patent_doc_number] => 20200144048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => WAFER PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 16/674203 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674203 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/674203
Wafer processing method using a ring frame and a polyester sheet Nov 4, 2019 Issued
Array ( [id] => 16132585 [patent_doc_number] => 10700060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => E-fuse for use in semiconductor device [patent_app_type] => utility [patent_app_number] => 16/671596 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6092 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671596 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671596
E-fuse for use in semiconductor device Oct 31, 2019 Issued
Array ( [id] => 17772516 [patent_doc_number] => 11404468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-02 [patent_title] => Wavelength tunable narrow band filter [patent_app_type] => utility [patent_app_number] => 16/654297 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 76 [patent_no_of_words] => 20527 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654297 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654297
Wavelength tunable narrow band filter Oct 15, 2019 Issued
Array ( [id] => 16781678 [patent_doc_number] => 20210118757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH FAN-OUT FEATURE [patent_app_type] => utility [patent_app_number] => 16/654187 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654187
Structure and formation method of chip package with fan-out feature Oct 15, 2019 Issued
Array ( [id] => 16781952 [patent_doc_number] => 20210119031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => TRANSISTOR HAVING WRAP-AROUND SOURCE/DRAIN CONTACTS AND UNDER-CONTACT SPACERS [patent_app_type] => utility [patent_app_number] => 16/654167 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654167 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654167
Transistor having wrap-around source/drain contacts and under-contact spacers Oct 15, 2019 Issued
Array ( [id] => 17270476 [patent_doc_number] => 11195906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Semiconductor device to suppress electric field concentration on insulating protection film [patent_app_type] => utility [patent_app_number] => 16/654181 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6093 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654181 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654181
Semiconductor device to suppress electric field concentration on insulating protection film Oct 15, 2019 Issued
Array ( [id] => 16781953 [patent_doc_number] => 20210119032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/654470 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654470 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654470
Method of manufacturing semiconductor devices and semiconductor devices Oct 15, 2019 Issued
Array ( [id] => 16781663 [patent_doc_number] => 20210118742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/654457 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654457 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654457
Method of manufacturing semiconductor devices having different gate dielectric thickness within one transistor Oct 15, 2019 Issued
Array ( [id] => 17878565 [patent_doc_number] => 11450588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Method for forming chip package structure with heat conductive layer [patent_app_type] => utility [patent_app_number] => 16/654198 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654198 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654198
Method for forming chip package structure with heat conductive layer Oct 15, 2019 Issued
Array ( [id] => 17590735 [patent_doc_number] => 11329012 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Semiconductor device having a conductive film on an inner wall of a through hole [patent_app_type] => utility [patent_app_number] => 16/654350 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5589 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/654350
Semiconductor device having a conductive film on an inner wall of a through hole Oct 15, 2019 Issued
Array ( [id] => 15462255 [patent_doc_number] => 20200043952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => METHOD OF PROVIDING AN IMAGING SYSTEM AND IMAGING SYSTEM THEREOF [patent_app_type] => utility [patent_app_number] => 16/601411 [patent_app_country] => US [patent_app_date] => 2019-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16601411 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/601411
Method of providing an imaging system and imaging system thereof Oct 13, 2019 Issued
Array ( [id] => 15807313 [patent_doc_number] => 20200126799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => WAFER PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 16/599502 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16599502 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/599502
Wafer processing method including applying a polyester sheet to a wafer Oct 10, 2019 Issued
Array ( [id] => 15746157 [patent_doc_number] => 20200111968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => ORGANIC ELECTROLUMINESCENCE DEVICE AND ELECTRONIC APPARATUS PROVIDED WITH THE SAME [patent_app_type] => utility [patent_app_number] => 16/593775 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16593775 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/593775
Organic electroluminescence device and electronic apparatus provided with the same Oct 3, 2019 Issued
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