Nilufa Rahim

Array ( [id] => 10302762 [patent_doc_number] => 20150187762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'SEMICONDUCTOR DEVICE WITH A MULTIPLE NANOWIRE CHANNEL STRUCTURE AND METHODS OF VARIABLY CONNECTING SUCH NANOWIRES FOR CURRENT DENSITY MODULATION' [patent_app_type] => utility [patent_app_number] => 14/146075 [patent_app_country] => US [patent_app_date] => 2014-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5812 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14146075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10294509 [patent_doc_number] => 20150179508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'Tantalum-Based Copper Barriers and Methods for Forming the Same' [patent_app_type] => utility [patent_app_number] => 14/138628 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10295477 [patent_doc_number] => 20150180477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'PORT SPREADING' [patent_app_type] => utility [patent_app_number] => 14/135693 [patent_app_country] => US [patent_app_date] => 2013-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3405 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14135693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9861894 [patent_doc_number] => 20150041912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-12 [patent_title] => 'Gate Stacks Including TaXSiYO for MOSFETS' [patent_app_type] => utility [patent_app_number] => 14/135381 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4743 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14135381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9565943 [patent_doc_number] => 20140183655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'HIGH PERFORMANCE ISOLATED VERTICAL BIPOLAR JUNCTION TRANSISTOR AND METHOD FOR FORMING IN A CMOS INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/134312 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10286054 [patent_doc_number] => 20150171052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'SUBSTRATE OF SEMICONDUCTOR AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/133366 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 864 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10047480 [patent_doc_number] => 09087886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/132306 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 8906 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10504242 [patent_doc_number] => 09232646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'High speed differential wiring in glass ceramic MCMS' [patent_app_type] => utility [patent_app_number] => 14/102832 [patent_app_country] => US [patent_app_date] => 2013-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6737 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9938047 [patent_doc_number] => 08987860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/103195 [patent_app_country] => US [patent_app_date] => 2013-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14103195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9809790 [patent_doc_number] => 20150021735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/092150 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3525 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14092150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9613538 [patent_doc_number] => 20140203395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/087554 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2433 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10504241 [patent_doc_number] => 09232645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'High speed differential wiring in glass ceramic MCMS' [patent_app_type] => utility [patent_app_number] => 14/087341 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6696 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9951768 [patent_doc_number] => 09000561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-07 [patent_title] => 'Patterned ground shield structures and semiconductor devices' [patent_app_type] => utility [patent_app_number] => 14/078946 [patent_app_country] => US [patent_app_date] => 2013-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14078946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9631935 [patent_doc_number] => 20140210044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-31 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING INDUCTOR' [patent_app_type] => utility [patent_app_number] => 14/076419 [patent_app_country] => US [patent_app_date] => 2013-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14076419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9836344 [patent_doc_number] => 20150028425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-29 [patent_title] => 'THREE DIMENSIONAL SEMICONDUCTOR DEVICE HAVING LATERAL CHANNEL AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/074452 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12535119 [patent_doc_number] => 10008566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Semiconductor device with reduced electrical resistance and capacitance [patent_app_type] => utility [patent_app_number] => 14/025041 [patent_app_country] => US [patent_app_date] => 2013-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 6088 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14025041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10583941 [patent_doc_number] => 09306069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Isolation structure of fin field effect transistor' [patent_app_type] => utility [patent_app_number] => 14/024148 [patent_app_country] => US [patent_app_date] => 2013-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14024148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9796547 [patent_doc_number] => 20150008490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-08 [patent_title] => 'Fluctuation Resistant FinFET' [patent_app_type] => utility [patent_app_number] => 14/024415 [patent_app_country] => US [patent_app_date] => 2013-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7528 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14024415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9716737 [patent_doc_number] => 20140252435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/021038 [patent_app_country] => US [patent_app_date] => 2013-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4090 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14021038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11578565 [patent_doc_number] => 09633835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Transistor fabrication technique including sacrificial protective layer for source/drain at contact location' [patent_app_type] => utility [patent_app_number] => 14/020299 [patent_app_country] => US [patent_app_date] => 2013-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9445 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14020299 [rel_patent_id] =>[rel_patent_doc_number] =>)