Search

Nilufa Rahim

Examiner (ID: 1665, Phone: (571)272-8926 , Office: P/2893 )

Most Active Art Unit
2893
Art Unit(s)
2893, RD00
Total Applications
618
Issued Applications
451
Pending Applications
99
Abandoned Applications
80

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19936789 [patent_doc_number] => 12310009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Read-only memory with vertical transistors [patent_app_type] => utility [patent_app_number] => 18/054835 [patent_app_country] => US [patent_app_date] => 2022-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2389 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18054835 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/054835
Read-only memory with vertical transistors Nov 10, 2022 Issued
Array ( [id] => 18475630 [patent_doc_number] => 20230209918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/981354 [patent_app_country] => US [patent_app_date] => 2022-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17981354 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/981354
DISPLAY DEVICE Nov 3, 2022 Pending
Array ( [id] => 20496775 [patent_doc_number] => 12538666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Display apparatus and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/977805 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 9974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17977805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/977805
Display apparatus and method of manufacturing the same Oct 30, 2022 Issued
Array ( [id] => 18655209 [patent_doc_number] => 20230301060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => THREE-DIMENSIONAL SILICON NANOSHEET MEMORY WITH METAL CAPACITOR [patent_app_type] => utility [patent_app_number] => 17/971219 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8158 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17971219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/971219
THREE-DIMENSIONAL SILICON NANOSHEET MEMORY WITH METAL CAPACITOR Oct 20, 2022 Abandoned
Array ( [id] => 20532004 [patent_doc_number] => 12550456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Trench gate metal oxide semiconductor field effect transistor and method of manufacture [patent_app_type] => utility [patent_app_number] => 17/970965 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17970965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/970965
Trench gate metal oxide semiconductor field effect transistor and method of manufacture Oct 20, 2022 Issued
Array ( [id] => 20692004 [patent_doc_number] => 12622179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Magnetic field-free spin-orbit torque switching device using sapphire miscut substrate [patent_app_type] => utility [patent_app_number] => 17/969146 [patent_app_country] => US [patent_app_date] => 2022-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17969146 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/969146
Magnetic field-free spin-orbit torque switching device using sapphire miscut substrate Oct 18, 2022 Issued
Array ( [id] => 18229511 [patent_doc_number] => 20230068505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => 3D SEMICONDUCTOR DEVICE AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/900073 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 49978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900073 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/900073
3D semiconductor device and structure Aug 30, 2022 Issued
Array ( [id] => 19859702 [patent_doc_number] => 12262579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Electroluminescence display having ultra high resolution [patent_app_type] => utility [patent_app_number] => 17/900488 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10384 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 487 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17900488 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/900488
Electroluminescence display having ultra high resolution Aug 30, 2022 Issued
Array ( [id] => 18081221 [patent_doc_number] => 20220406833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => PHOTODETECTOR WITH BURIED AIRGAP REFLECTORS [patent_app_type] => utility [patent_app_number] => 17/896401 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896401
Photodetector with buried airgap reflectors Aug 25, 2022 Issued
Array ( [id] => 18097529 [patent_doc_number] => 20220415870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => PIXEL STRUCTURE, DISPLAY DEVICE INCLUDING THE PIXEL STRUCTURE, AND METHOD OF MANUFACTURING THE PIXEL STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/821462 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821462 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/821462
Pixel structure, display device including the pixel structure, and method of manufacturing the pixel structure Aug 21, 2022 Issued
Array ( [id] => 18655240 [patent_doc_number] => 20230301091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/891655 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891655
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE Aug 18, 2022 Pending
Array ( [id] => 20484257 [patent_doc_number] => 12532738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Chip package structure with heat conductive layer [patent_app_type] => utility [patent_app_number] => 17/818437 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 2104 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818437 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818437
Chip package structure with heat conductive layer Aug 8, 2022 Issued
Array ( [id] => 18040200 [patent_doc_number] => 20220384417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => METHOD OF SEMICONDUCTOR LAYOUT WITH DIFFERENT ROW HEIGHTS [patent_app_type] => utility [patent_app_number] => 17/884293 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884293 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884293
Method of semiconductor layout with different row heights Aug 8, 2022 Issued
Array ( [id] => 18421644 [patent_doc_number] => 20230176108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF TESTING THE SAME [patent_app_type] => utility [patent_app_number] => 17/816619 [patent_app_country] => US [patent_app_date] => 2022-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816619 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/816619
Semiconductor package and method of testing the same Jul 31, 2022 Issued
Array ( [id] => 20531918 [patent_doc_number] => 12550370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/876331 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 77 [patent_no_of_words] => 6830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876331 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876331
Semiconductor device and manufacturing method thereof Jul 27, 2022 Issued
Array ( [id] => 20276505 [patent_doc_number] => 12446294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Method of manufacturing semiconductor devices having different gate dielectric thickness within one transistor [patent_app_type] => utility [patent_app_number] => 17/874279 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 3474 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874279
Method of manufacturing semiconductor devices having different gate dielectric thickness within one transistor Jul 25, 2022 Issued
Array ( [id] => 17993265 [patent_doc_number] => 20220359302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR DEVICE HAVING CUT GATE DIELECTRIC [patent_app_type] => utility [patent_app_number] => 17/872103 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872103 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872103
Semiconductor device having cut gate dielectric Jul 24, 2022 Issued
Array ( [id] => 17993166 [patent_doc_number] => 20220359203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => LINE-END EXTENSION METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/869707 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869707 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869707
Line-end extension method and device Jul 19, 2022 Issued
Array ( [id] => 17984225 [patent_doc_number] => 20220350262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => Multi-Metal Fill with Self-Aligned Patterning and Dielectric with Voids [patent_app_type] => utility [patent_app_number] => 17/868398 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868398 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868398
Multi-metal fill with self-aligned patterning and dielectric with voids Jul 18, 2022 Issued
Array ( [id] => 17963618 [patent_doc_number] => 20220344199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => INTEGRATED CIRCUIT ISOLATION FEATURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/860264 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860264
Integrated circuit isolation feature and method of forming the same Jul 7, 2022 Issued
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