Search

Nina Nmn Bhat

Examiner (ID: 2197, Phone: (571)272-1397 , Office: P/3649 )

Most Active Art Unit
1761
Art Unit(s)
1761, 1764, 1771, 3649, 1754, 1809, 1797, 1312, 2204, 1801, 2203
Total Applications
3486
Issued Applications
2769
Pending Applications
205
Abandoned Applications
519

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20013152 [patent_doc_number] => 20250151374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => ELECTRICAL CONTACT CAVITY STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/887821 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887821 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/887821
Electrical contact cavity structure and methods of forming the same Sep 16, 2024 Issued
Array ( [id] => 19531979 [patent_doc_number] => 20240355881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH NANOSTRUCTURE [patent_app_type] => utility [patent_app_number] => 18/758898 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758898 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758898
Semiconductor device structure with nanostructure Jun 27, 2024 Issued
Array ( [id] => 19515707 [patent_doc_number] => 20240347393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => Gate Structures For Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 18/754468 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754468 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754468
Gate Structures For Semiconductor Devices Jun 25, 2024 Pending
Array ( [id] => 19515854 [patent_doc_number] => 20240347540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEMICONDUCTOR DEVICES INCLUDING TWO-DIMENSIONAL MATERIAL AND METHODS OF FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/752906 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752906 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752906
SEMICONDUCTOR DEVICES INCLUDING TWO-DIMENSIONAL MATERIAL AND METHODS OF FABRICATION THEREOF Jun 24, 2024 Pending
Array ( [id] => 20217688 [patent_doc_number] => 12414357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Self-aligned metal gate for multigate device [patent_app_type] => utility [patent_app_number] => 18/752112 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 19614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752112 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752112
Self-aligned metal gate for multigate device Jun 23, 2024 Issued
Array ( [id] => 20334505 [patent_doc_number] => 12464801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Circuit structure with gate configuration [patent_app_type] => utility [patent_app_number] => 18/752321 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 4716 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752321
Circuit structure with gate configuration Jun 23, 2024 Issued
Array ( [id] => 20260599 [patent_doc_number] => 12432970 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Semiconductor devices with backside power rail and backside self-aligned via [patent_app_type] => utility [patent_app_number] => 18/746288 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 91 [patent_no_of_words] => 7444 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746288 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746288
Semiconductor devices with backside power rail and backside self-aligned via Jun 17, 2024 Issued
Array ( [id] => 20205581 [patent_doc_number] => 12408377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Semiconductor device structure with backside contact [patent_app_type] => utility [patent_app_number] => 18/745029 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 38 [patent_no_of_words] => 6192 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745029 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745029
Semiconductor device structure with backside contact Jun 16, 2024 Issued
Array ( [id] => 19500526 [patent_doc_number] => 20240339544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => LIGHTLY-DOPED CHANNEL EXTENSIONS [patent_app_type] => utility [patent_app_number] => 18/744952 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744952 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744952
LIGHTLY-DOPED CHANNEL EXTENSIONS Jun 16, 2024 Pending
Array ( [id] => 20435966 [patent_doc_number] => 12507440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Multi-layer channel structures and methods of fabricating the same in field-effect transistors [patent_app_type] => utility [patent_app_number] => 18/742126 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 67 [patent_no_of_words] => 4559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742126 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742126
Multi-layer channel structures and methods of fabricating the same in field-effect transistors Jun 12, 2024 Issued
Array ( [id] => 19500524 [patent_doc_number] => 20240339542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => Semiconductor Devices Including Backside Vias and Methods of Forming the Same [patent_app_type] => utility [patent_app_number] => 18/741987 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741987 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741987
Semiconductor devices including backside vias and methods of forming the same Jun 12, 2024 Issued
Array ( [id] => 20390735 [patent_doc_number] => 12490483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Semiconductor devices and methods of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 18/741356 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 3209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741356 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741356
Semiconductor devices and methods of manufacturing thereof Jun 11, 2024 Issued
Array ( [id] => 20346051 [patent_doc_number] => 12469786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Integrated circuit and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/740024 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 126 [patent_figures_cnt] => 135 [patent_no_of_words] => 10825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740024 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740024
Integrated circuit and method for forming the same Jun 10, 2024 Issued
Array ( [id] => 20267044 [patent_doc_number] => 12438043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Semiconductor structure with staggered selective growth [patent_app_type] => utility [patent_app_number] => 18/738390 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 4508 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738390 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/738390
Semiconductor structure with staggered selective growth Jun 9, 2024 Issued
Array ( [id] => 19468323 [patent_doc_number] => 20240321993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => NANOWIRE TRANSISTOR AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/679459 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679459
Nanowire transistor and method for fabricating the same May 30, 2024 Issued
Array ( [id] => 20177483 [patent_doc_number] => 12396248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Semiconductor device fabrication methods and structures thereof [patent_app_type] => utility [patent_app_number] => 18/673960 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 40 [patent_no_of_words] => 6538 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673960
Semiconductor device fabrication methods and structures thereof May 23, 2024 Issued
Array ( [id] => 19452864 [patent_doc_number] => 20240312994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => GAP-INSULATED SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/672218 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672218 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672218
Gap-insulated semiconductor device May 22, 2024 Issued
Array ( [id] => 19452937 [patent_doc_number] => 20240313067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => EFFECTIVE WORK FUNCTION TUNING VIA SILICIDE INDUCED INTERFACE DIPOLE MODULATION FOR METAL GATES [patent_app_type] => utility [patent_app_number] => 18/669199 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669199
Effective work function tuning via silicide induced interface dipole modulation for metal gates May 19, 2024 Issued
Array ( [id] => 19452952 [patent_doc_number] => 20240313082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => AIR GAP IN INNER SPACERS AND METHODS OF FABRICATING THE SAME IN FIELD-EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/669052 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18669052 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/669052
Air gap in inner spacers and methods of fabricating the same in field-effect transistors May 19, 2024 Issued
Array ( [id] => 19828860 [patent_doc_number] => 12249656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Transistor, integrated circuit, and manufacturing method of transistor [patent_app_type] => utility [patent_app_number] => 18/665572 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 55 [patent_no_of_words] => 9669 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/665572
Transistor, integrated circuit, and manufacturing method of transistor May 15, 2024 Issued
Menu