Search

Nina Nmn Bhat

Examiner (ID: 12197, Phone: (571)272-1397 , Office: P/3649 )

Most Active Art Unit
1761
Art Unit(s)
3649, 1754, 1761, 2204, 1801, 1764, 1771, 1312, 1797, 2203, 1809
Total Applications
3486
Issued Applications
2769
Pending Applications
205
Abandoned Applications
519

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18226029 [patent_doc_number] => 20230065023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => STATION APPARATUS AND COMMUNICATION METHOD [patent_app_type] => utility [patent_app_number] => 17/795831 [patent_app_country] => US [patent_app_date] => 2021-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14106 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17795831 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/795831
STATION APPARATUS AND COMMUNICATION METHOD Feb 16, 2021 Abandoned
Array ( [id] => 16872245 [patent_doc_number] => 20210165712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => DYNAMIC SELF-CORRECTION OF MESSAGE RELIABILITY IN LDPC CODES [patent_app_type] => utility [patent_app_number] => 17/171430 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171430 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171430
Dynamic self-correction of message reliability in LDPC codes Feb 8, 2021 Issued
Array ( [id] => 16979913 [patent_doc_number] => 20210224150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => FAULT TOLERANT COMPUTATION METHOD AND APPARATUS FOR QUANTUM CLIFFORD CIRCUIT, DEVICE, AND CHIP [patent_app_type] => utility [patent_app_number] => 17/167932 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167932 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167932
Fault tolerant computation method and apparatus for quantum Clifford circuit, device, and chip Feb 3, 2021 Issued
Array ( [id] => 17763466 [patent_doc_number] => 20220237078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => MITIGATING READ DISTURB EFFECTS IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/160194 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160194
Mitigating read disturb effects in memory devices Jan 26, 2021 Issued
Array ( [id] => 17817102 [patent_doc_number] => 11422713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Memory error indicator for high-reliability applications [patent_app_type] => utility [patent_app_number] => 17/157797 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 16877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157797
Memory error indicator for high-reliability applications Jan 24, 2021 Issued
Array ( [id] => 17826396 [patent_doc_number] => 11431355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Error correction code (ECC) operations in memory for providing redundant error correction [patent_app_type] => utility [patent_app_number] => 17/157141 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157141 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157141
Error correction code (ECC) operations in memory for providing redundant error correction Jan 24, 2021 Issued
Array ( [id] => 17758533 [patent_doc_number] => 11398836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Dynamically variable error correcting code (ECC) system with hybrid rateless reed-solomon ECCs [patent_app_type] => utility [patent_app_number] => 17/154739 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17154739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/154739
Dynamically variable error correcting code (ECC) system with hybrid rateless reed-solomon ECCs Jan 20, 2021 Issued
Array ( [id] => 18121251 [patent_doc_number] => 11552654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Forward error control coding [patent_app_type] => utility [patent_app_number] => 17/141095 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141095 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141095
Forward error control coding Jan 3, 2021 Issued
Array ( [id] => 17818379 [patent_doc_number] => 11424000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Test system for executing built-in self-test in deployment for automotive applications [patent_app_type] => utility [patent_app_number] => 17/133781 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9707 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133781 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133781
Test system for executing built-in self-test in deployment for automotive applications Dec 23, 2020 Issued
Array ( [id] => 18218257 [patent_doc_number] => 11593195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Configurable integrated circuit (IC) with cyclic redundancy check (CRC) arbitration [patent_app_type] => utility [patent_app_number] => 17/128595 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7680 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128595
Configurable integrated circuit (IC) with cyclic redundancy check (CRC) arbitration Dec 20, 2020 Issued
Array ( [id] => 18143751 [patent_doc_number] => 20230017602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => TRACKING CHARGE LOSS IN MEMORY SUB-SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/419107 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17419107 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/419107
Tracking charge loss in memory sub-systems Dec 17, 2020 Issued
Array ( [id] => 17439677 [patent_doc_number] => 11265022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-01 [patent_title] => Memory system and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/109297 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 10358 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109297
Memory system and operating method thereof Dec 1, 2020 Issued
Array ( [id] => 17970080 [patent_doc_number] => 11487613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Method for accessing semiconductor memory module [patent_app_type] => utility [patent_app_number] => 17/105821 [patent_app_country] => US [patent_app_date] => 2020-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12164 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105821 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105821
Method for accessing semiconductor memory module Nov 26, 2020 Issued
Array ( [id] => 19705588 [patent_doc_number] => 12199638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Information concealing apparatus, information reconfiguring apparatus, information concealing system, information concealing method, information reconfiguring method, information concealing program, and information reconfiguring program [patent_app_type] => utility [patent_app_number] => 18/034548 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12699 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18034548 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/034548
Information concealing apparatus, information reconfiguring apparatus, information concealing system, information concealing method, information reconfiguring method, information concealing program, and information reconfiguring program Nov 16, 2020 Issued
Array ( [id] => 16690592 [patent_doc_number] => 20210073070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => METHODS AND SYSTEM WITH DYNAMIC ECC VOLTAGE AND FREQUENCY [patent_app_type] => utility [patent_app_number] => 17/099389 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17099389 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/099389
Methods and system with dynamic ECC voltage and frequency Nov 15, 2020 Issued
Array ( [id] => 16658708 [patent_doc_number] => 20210055345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SCAN CHAIN SELF-TESTING OF LOCKSTEP CORES ON RESET [patent_app_type] => utility [patent_app_number] => 17/093702 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093702 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093702
Scan chain self-testing of lockstep cores on reset Nov 9, 2020 Issued
Array ( [id] => 18079556 [patent_doc_number] => 20220405168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => CONTROLLER AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/777915 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17777915 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/777915
Controller and storage device Nov 4, 2020 Issued
Array ( [id] => 18904709 [patent_doc_number] => 20240020194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => ERROR DETECTION, PREDICTION AND HANDLING TECHNIQUES FOR SYSTEM-IN-PACKAGE MEMORY ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/035498 [patent_app_country] => US [patent_app_date] => 2020-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18035498 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/035498
Error detection, prediction and handling techniques for system-in-package memory architectures Nov 3, 2020 Issued
Array ( [id] => 16758577 [patent_doc_number] => 10977127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => Concatenating data objects in a vast data storage network [patent_app_type] => utility [patent_app_number] => 17/081056 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 70 [patent_no_of_words] => 44016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081056 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081056
Concatenating data objects in a vast data storage network Oct 26, 2020 Issued
Array ( [id] => 16623532 [patent_doc_number] => 20210042185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => ERROR CORRECTION IN ROW HAMMER MITIGATION AND TARGET ROW REFRESH [patent_app_type] => utility [patent_app_number] => 17/080238 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080238 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080238
Error correction in row hammer mitigation and target row refresh Oct 25, 2020 Issued
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