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Nina Nmn Bhat

Examiner (ID: 2197, Phone: (571)272-1397 , Office: P/3649 )

Most Active Art Unit
1761
Art Unit(s)
1761, 1764, 1771, 3649, 1754, 1809, 1797, 1312, 2204, 1801, 2203
Total Applications
3486
Issued Applications
2769
Pending Applications
205
Abandoned Applications
519

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19237554 [patent_doc_number] => 20240194749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/581096 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581096 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581096
Semiconductor devices Feb 18, 2024 Issued
Array ( [id] => 19221674 [patent_doc_number] => 20240186378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING EMBEDDED GESNB SOURCE OR DRAIN STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/440526 [patent_app_country] => US [patent_app_date] => 2024-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14555 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18440526 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/440526
Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures Feb 12, 2024 Issued
Array ( [id] => 19906612 [patent_doc_number] => 12283631 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Method of manufacturing a semiconductor device and a semiconductor device [patent_app_type] => utility [patent_app_number] => 18/437625 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 64 [patent_no_of_words] => 5867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437625 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/437625
Method of manufacturing a semiconductor device and a semiconductor device Feb 8, 2024 Issued
Array ( [id] => 20229265 [patent_doc_number] => 12417920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Transistor gate structure and method of forming [patent_app_type] => utility [patent_app_number] => 18/435140 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 61 [patent_no_of_words] => 7914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/435140
Transistor gate structure and method of forming Feb 6, 2024 Issued
Array ( [id] => 19906593 [patent_doc_number] => 12283612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-22 [patent_title] => Metal oxide and transistor including metal oxide [patent_app_type] => utility [patent_app_number] => 18/430771 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 90 [patent_no_of_words] => 43617 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430771 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430771
Metal oxide and transistor including metal oxide Feb 1, 2024 Issued
Array ( [id] => 19191630 [patent_doc_number] => 20240170543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => PROCESS WINDOW CONTROL FOR GATE FORMATION IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/426859 [patent_app_country] => US [patent_app_date] => 2024-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/426859
Process window control for gate formation in semiconductor devices Jan 29, 2024 Issued
Array ( [id] => 19912595 [patent_doc_number] => 12288814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-29 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 18/421398 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 11685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421398 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/421398
Semiconductor device and method of manufacture Jan 23, 2024 Issued
Array ( [id] => 19887021 [patent_doc_number] => 12272755 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 18/420327 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 7660 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420327 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420327
Semiconductor structure Jan 22, 2024 Issued
Array ( [id] => 19221475 [patent_doc_number] => 20240186179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => Methods of Forming Spacers for Semiconductor Devices Including Backside Power Rails [patent_app_type] => utility [patent_app_number] => 18/420209 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18420209 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/420209
Methods of forming spacers for semiconductor devices including backside power rails Jan 22, 2024 Issued
Array ( [id] => 19176329 [patent_doc_number] => 20240162303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => Gate Structures in Transistors and Method of Forming Same [patent_app_type] => utility [patent_app_number] => 18/418678 [patent_app_country] => US [patent_app_date] => 2024-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/418678
Gate structures in transistors and method of forming same Jan 21, 2024 Issued
Array ( [id] => 20305361 [patent_doc_number] => 12451359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Fluorine incorporation method for nanosheet [patent_app_type] => utility [patent_app_number] => 18/412173 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 53 [patent_figures_cnt] => 65 [patent_no_of_words] => 9023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412173 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412173
Fluorine incorporation method for nanosheet Jan 11, 2024 Issued
Array ( [id] => 19148576 [patent_doc_number] => 20240147694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MEMORY CELL AND SEMICONDUCTOR MEMORY DEVICE WITH THE SAME [patent_app_type] => utility [patent_app_number] => 18/411031 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411031 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411031
Memory cell and semiconductor memory device with the same Jan 11, 2024 Issued
Array ( [id] => 19900300 [patent_doc_number] => 12278238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/404874 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 65 [patent_no_of_words] => 8546 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404874 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404874
Semiconductor structure and method of forming the same Jan 3, 2024 Issued
Array ( [id] => 19116597 [patent_doc_number] => 20240128347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/397700 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397700
Semiconductor device Dec 26, 2023 Issued
Array ( [id] => 19086381 [patent_doc_number] => 20240113182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/538575 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/538575
Integrated circuit device Dec 12, 2023 Issued
Array ( [id] => 19539397 [patent_doc_number] => 12131954 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-29 [patent_title] => Selective epitaxy process for the formation of CFET local interconnection [patent_app_type] => utility [patent_app_number] => 18/531047 [patent_app_country] => US [patent_app_date] => 2023-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 7286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18531047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/531047
Selective epitaxy process for the formation of CFET local interconnection Dec 5, 2023 Issued
Array ( [id] => 20268667 [patent_doc_number] => 12439680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Multi-gate device and related methods [patent_app_type] => utility [patent_app_number] => 18/526839 [patent_app_country] => US [patent_app_date] => 2023-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 6947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18526839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/526839
Multi-gate device and related methods Nov 30, 2023 Issued
Array ( [id] => 19868391 [patent_doc_number] => 20250107177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => Nanosheet Sizing for Power Delivery [patent_app_type] => utility [patent_app_number] => 18/524600 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524600 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524600
Nanosheet sizing for power delivery Nov 29, 2023 Issued
Array ( [id] => 20334512 [patent_doc_number] => 12464808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Dummy cell designs for nanosheet devices [patent_app_type] => utility [patent_app_number] => 18/524529 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524529 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524529
Dummy cell designs for nanosheet devices Nov 29, 2023 Issued
Array ( [id] => 19886918 [patent_doc_number] => 12272649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 18/522980 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 15264 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/522980
Semiconductor device and method Nov 28, 2023 Issued
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