Nina Nmn Bhat

Array ( [id] => 18515293 [patent_doc_number] => 20230231575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => Systems and Methods for Decoding of Graph-Based Channel Codes Via Reinforcement Learning [patent_app_type] => utility [patent_app_number] => 17/954120 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19052952 [patent_doc_number] => 20240094921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => TESTING OPERATIONS FOR MEMORY SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/949867 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18741772 [patent_doc_number] => 20230350753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => STORAGE SYSTEM AND FAILURE HANDLING METHOD [patent_app_type] => utility [patent_app_number] => 17/946632 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18239453 [patent_doc_number] => 20230071764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => ERROR CACHING TECHNIQUES FOR IMPROVED ERROR CORRECTION IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/943581 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18515295 [patent_doc_number] => 20230231577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => METHOD AND SYSTEM FOR POLAR CODE CODING [patent_app_type] => utility [patent_app_number] => 17/942885 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19037851 [patent_doc_number] => 20240087666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => Mitigation of transistor reliability degradation within memory circuits [patent_app_type] => utility [patent_app_number] => 17/942143 [patent_app_country] => US [patent_app_date] => 2022-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942143 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19005951 [patent_doc_number] => 20240070022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => DATA INVERSION AND UNIDIRECTIONAL ERROR DETECTION [patent_app_type] => utility [patent_app_number] => 17/897186 [patent_app_country] => US [patent_app_date] => 2022-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18513324 [patent_doc_number] => 20230229554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => METHOD AND SYSTEM FOR ON-ASIC ERROR CONTROL ENCODING [patent_app_type] => utility [patent_app_number] => 17/894742 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894742 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18067981 [patent_doc_number] => 20220399069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => Test System For Executing Built-In Self-Test In Deployment For Automotive Applications [patent_app_type] => utility [patent_app_number] => 17/892336 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18062613 [patent_doc_number] => 20220393700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => ZERO PADDING APPARATUS FOR ENCODING FIXED-LENGTH SIGNALING INFORMATION AND ZERO PADDING METHOD USING SAME [patent_app_type] => utility [patent_app_number] => 17/891189 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891189 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18221915 [patent_doc_number] => 20230060909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => EARLY DETECTION OF QUALITY CONTROL TEST FAILURES FOR MANUFACTURING END-TO-END TESTING OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 17/891405 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19413262 [patent_doc_number] => 12079078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Command address fault detection [patent_app_type] => utility [patent_app_number] => 17/820120 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11247 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18038410 [patent_doc_number] => 20220382626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => QUANTUM ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 17/819522 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5975 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19375322 [patent_doc_number] => 12066887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Reducing cryptographic update errors in memory devices using cyclical redundancy checks [patent_app_type] => utility [patent_app_number] => 17/887346 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18041117 [patent_doc_number] => 20220385334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => TRANSMISSION OF PULSE POWER AND DATA IN A COMMUNICATIONS NETWORK [patent_app_type] => utility [patent_app_number] => 17/884124 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18007080 [patent_doc_number] => 20220365846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => INTEGRATED CIRCUIT AND METHOD OF OPERATING SAME [patent_app_type] => utility [patent_app_number] => 17/816085 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18993 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18166067 [patent_doc_number] => 20230032668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => CONFIGURABLE DATA PATH FOR MEMORY MODULES [patent_app_type] => utility [patent_app_number] => 17/877706 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18365636 [patent_doc_number] => 20230147227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => MEMORY CONTROLLERS, MEMORY SYSTEMS, AND MEMORY MODULES [patent_app_type] => utility [patent_app_number] => 17/814964 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17814964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18944418 [patent_doc_number] => 20240039557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => Receiver with Duty Cycled Listening [patent_app_type] => utility [patent_app_number] => 17/873844 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18577580 [patent_doc_number] => 11734112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/869881 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 40 [patent_no_of_words] => 34411 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869881 [rel_patent_id] =>[rel_patent_doc_number] =>)