Search

Nina Nmn Bhat

Examiner (ID: 2197, Phone: (571)272-1397 , Office: P/3649 )

Most Active Art Unit
1761
Art Unit(s)
1761, 1764, 1771, 3649, 1754, 1809, 1797, 1312, 2204, 1801, 2203
Total Applications
3486
Issued Applications
2769
Pending Applications
205
Abandoned Applications
519

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19524180 [patent_doc_number] => 12125921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Semiconducting metal oxide transistors having a patterned gate and methods for forming the same [patent_app_type] => utility [patent_app_number] => 18/354681 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 33 [patent_no_of_words] => 13808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354681 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354681
Semiconducting metal oxide transistors having a patterned gate and methods for forming the same Jul 18, 2023 Issued
Array ( [id] => 19452863 [patent_doc_number] => 20240312993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SINGLE METAL GATE WITH DUAL EFFECTIVE WORK FUNCTION GATE METAL SCHEME [patent_app_type] => utility [patent_app_number] => 18/354515 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8736 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354515 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354515
SINGLE METAL GATE WITH DUAL EFFECTIVE WORK FUNCTION GATE METAL SCHEME Jul 17, 2023 Pending
Array ( [id] => 19494392 [patent_doc_number] => 12113116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/352876 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 64 [patent_no_of_words] => 11623 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352876
Semiconductor device and manufacturing method thereof Jul 13, 2023 Issued
Array ( [id] => 19568310 [patent_doc_number] => 12143093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Substrate for a temperature-compensated surface acoustic wave device or volume acoustic wave device [patent_app_type] => utility [patent_app_number] => 18/352972 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3854 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352972 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352972
Substrate for a temperature-compensated surface acoustic wave device or volume acoustic wave device Jul 13, 2023 Issued
Array ( [id] => 18759656 [patent_doc_number] => 20230363145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => CAPACITOR, MEMORY DEVICE, AND METHOD [patent_app_type] => utility [patent_app_number] => 18/352738 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352738
Capacitor, memory device, and method Jul 13, 2023 Issued
Array ( [id] => 19285973 [patent_doc_number] => 20240222450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/221479 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221479 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221479
SEMICONDUCTOR DEVICE Jul 12, 2023 Pending
Array ( [id] => 18743564 [patent_doc_number] => 20230352552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Memory, Gate-All-Around Field-Effect Transistor, and Manufacturing Method [patent_app_type] => utility [patent_app_number] => 18/350348 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350348 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350348
Memory, Gate-All-Around Field-Effect Transistor, and Manufacturing Method Jul 10, 2023 Pending
Array ( [id] => 19101050 [patent_doc_number] => 20240120278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/219140 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18219140 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/219140
Semiconductor device Jul 6, 2023 Issued
Array ( [id] => 18743565 [patent_doc_number] => 20230352553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => GATE STRUCTURE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/347480 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347480 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347480
Gate structure and method Jul 4, 2023 Issued
Array ( [id] => 18729490 [patent_doc_number] => 20230343786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/347023 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347023 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347023
Semiconductor devices Jul 4, 2023 Issued
Array ( [id] => 18743431 [patent_doc_number] => 20230352419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 18/346887 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18346887 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/346887
Semiconductor packages Jul 4, 2023 Issued
Array ( [id] => 19507978 [patent_doc_number] => 12119409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Multi-layer crystalline back gated thin film transistor [patent_app_type] => utility [patent_app_number] => 18/345641 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345641
Multi-layer crystalline back gated thin film transistor Jun 29, 2023 Issued
Array ( [id] => 19446316 [patent_doc_number] => 12096629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Floating gate test structure for embedded memory device [patent_app_type] => utility [patent_app_number] => 18/344161 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 10066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344161
Floating gate test structure for embedded memory device Jun 28, 2023 Issued
Array ( [id] => 19662212 [patent_doc_number] => 20240429277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => MULTIPLE GATE DIELECTRICS FOR MONOLITHIC STACKED DEVICES [patent_app_type] => utility [patent_app_number] => 18/213493 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213493 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213493
MULTIPLE GATE DIELECTRICS FOR MONOLITHIC STACKED DEVICES Jun 22, 2023 Pending
Array ( [id] => 18729551 [patent_doc_number] => 20230343847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => GATE STRUCTURE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/340758 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340758 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/340758
Gate structure and method Jun 22, 2023 Issued
Array ( [id] => 19662235 [patent_doc_number] => 20240429300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => GATE-ALL-AROUND (GAA) FIELD-EFFECT TRANSISTOR (FET) DEVICE HAVING FETs WITH DIFFERENT CRYSTALLINE ORIENTATION CHANNELS THROUGH A SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/339349 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18339349 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/339349
GATE-ALL-AROUND (GAA) FIELD-EFFECT TRANSISTOR (FET) DEVICE HAVING FETs WITH DIFFERENT CRYSTALLINE ORIENTATION CHANNELS THROUGH A SUBSTRATE Jun 21, 2023 Pending
Array ( [id] => 18714790 [patent_doc_number] => 20230337435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => 3D HYBRID MEMORY USING HORIZONTALLY ORIENTED CONDUCTIVE DIELECTRIC CHANNEL REGIONS [patent_app_type] => utility [patent_app_number] => 18/336678 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336678
3D HYBRID MEMORY USING HORIZONTALLY ORIENTED CONDUCTIVE DIELECTRIC CHANNEL REGIONS Jun 15, 2023 Pending
Array ( [id] => 18696411 [patent_doc_number] => 20230326850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => Semiconductor Device and Method of Manufacture [patent_app_type] => utility [patent_app_number] => 18/334843 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334843 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334843
Semiconductor device and method of manufacture Jun 13, 2023 Issued
Array ( [id] => 19646440 [patent_doc_number] => 20240420960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => INVERTED GATE CUT REGION [patent_app_type] => utility [patent_app_number] => 18/333832 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333832 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333832
INVERTED GATE CUT REGION Jun 12, 2023 Pending
Array ( [id] => 19229660 [patent_doc_number] => 12009304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Integrated circuit and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/334136 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 126 [patent_figures_cnt] => 135 [patent_no_of_words] => 15207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334136 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334136
Integrated circuit and method for forming the same Jun 12, 2023 Issued
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