Search

Nina Nmn Bhat

Examiner (ID: 12197, Phone: (571)272-1397 , Office: P/3649 )

Most Active Art Unit
1761
Art Unit(s)
3649, 1754, 1761, 2204, 1801, 1764, 1771, 1312, 1797, 2203, 1809
Total Applications
3486
Issued Applications
2769
Pending Applications
205
Abandoned Applications
519

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18872927 [patent_doc_number] => 11860734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Semiconductor memory devices and memory systems [patent_app_type] => utility [patent_app_number] => 17/736154 [patent_app_country] => US [patent_app_date] => 2022-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736154 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/736154
Semiconductor memory devices and memory systems May 3, 2022 Issued
Array ( [id] => 18356750 [patent_doc_number] => 11645151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-09 [patent_title] => Base die, memory system, and semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/661604 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 9884 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17661604 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/661604
Base die, memory system, and semiconductor structure May 1, 2022 Issued
Array ( [id] => 18968122 [patent_doc_number] => 11901914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Low-density parity-check (LDPC) encoding method and apparatus [patent_app_type] => utility [patent_app_number] => 17/732776 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 15112 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17732776 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/732776
Low-density parity-check (LDPC) encoding method and apparatus Apr 28, 2022 Issued
Array ( [id] => 18857045 [patent_doc_number] => 11854636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Data sampling circuit and semiconductor memory [patent_app_type] => utility [patent_app_number] => 17/733030 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9888 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733030
Data sampling circuit and semiconductor memory Apr 28, 2022 Issued
Array ( [id] => 18919576 [patent_doc_number] => 11881872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Computational memory with zero disable and error detection [patent_app_type] => utility [patent_app_number] => 17/733338 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 13180 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733338
Computational memory with zero disable and error detection Apr 28, 2022 Issued
Array ( [id] => 18386153 [patent_doc_number] => 11656934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Managing open blocks in memory systems [patent_app_type] => utility [patent_app_number] => 17/730548 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 12854 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730548 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730548
Managing open blocks in memory systems Apr 26, 2022 Issued
Array ( [id] => 18414837 [patent_doc_number] => 11669379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Controller that receives a cyclic redundancy check (CRC) code for both read and write data transmitted via bidirectional data link [patent_app_type] => utility [patent_app_number] => 17/728621 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/728621
Controller that receives a cyclic redundancy check (CRC) code for both read and write data transmitted via bidirectional data link Apr 24, 2022 Issued
Array ( [id] => 18727952 [patent_doc_number] => 20230342245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => IMAGE MODELS TO PREDICT MEMORY FAILURES IN COMPUTING SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/727454 [patent_app_country] => US [patent_app_date] => 2022-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6400 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727454 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/727454
Image models to predict memory failures in computing systems Apr 21, 2022 Issued
Array ( [id] => 18727949 [patent_doc_number] => 20230342242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => ERROR CORRECTION CODE VALIDATION [patent_app_type] => utility [patent_app_number] => 17/726123 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726123 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726123
Error correction code validation Apr 20, 2022 Issued
Array ( [id] => 18378113 [patent_doc_number] => 20230153200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => MEMORY SYSTEM, MEMORY CONTROLLER AND OPERATING METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/726256 [patent_app_country] => US [patent_app_date] => 2022-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17726256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/726256
Memory system, memory controller and operating method of memory system Apr 20, 2022 Issued
Array ( [id] => 18720033 [patent_doc_number] => 11797378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Multichip package link error detection [patent_app_type] => utility [patent_app_number] => 17/721290 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 17932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/721290
Multichip package link error detection Apr 13, 2022 Issued
Array ( [id] => 18408684 [patent_doc_number] => 20230170037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => HYBRID MEMORY SYSTEM WITH INCREASED BANDWIDTH [patent_app_type] => utility [patent_app_number] => 17/658846 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -34 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/658846
Hybrid memory system with increased bandwidth Apr 11, 2022 Issued
Array ( [id] => 17751523 [patent_doc_number] => 20220229728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => REDUCED PARITY DATA MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/712978 [patent_app_country] => US [patent_app_date] => 2022-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8899 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712978 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712978
Reduced parity data management Apr 3, 2022 Issued
Array ( [id] => 19228800 [patent_doc_number] => 12008438 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-11 [patent_title] => Lattice surgery techniques using twists [patent_app_type] => utility [patent_app_number] => 17/707811 [patent_app_country] => US [patent_app_date] => 2022-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 49 [patent_no_of_words] => 18588 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17707811 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/707811
Lattice surgery techniques using twists Mar 28, 2022 Issued
Array ( [id] => 18608734 [patent_doc_number] => 11750221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-05 [patent_title] => Encoding and decoding of data using generalized LDPC codes [patent_app_type] => utility [patent_app_number] => 17/706179 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706179
Encoding and decoding of data using generalized LDPC codes Mar 27, 2022 Issued
Array ( [id] => 18659916 [patent_doc_number] => 20230305923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => Error-Tolerant Memory System for Machine Learning Systems [patent_app_type] => utility [patent_app_number] => 17/704474 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704474 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704474
Error-tolerant memory system for machine learning systems Mar 24, 2022 Issued
Array ( [id] => 17722219 [patent_doc_number] => 20220214941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => Method and System for Identifying Erased Memory Areas [patent_app_type] => utility [patent_app_number] => 17/705122 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705122 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705122
Method and system for identifying erased memory areas Mar 24, 2022 Issued
Array ( [id] => 18659914 [patent_doc_number] => 20230305921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => MULTIPLE BIT ERROR DETECTION IN SCRUB OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/655955 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14622 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/655955
Multiple bit error detection in scrub operations Mar 21, 2022 Issued
Array ( [id] => 18652841 [patent_doc_number] => 20230298681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => METHOD AND SYSTEM FOR TESTING OF MEMORY [patent_app_type] => utility [patent_app_number] => 17/655389 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3164 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17655389 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/655389
Method and system for testing of memory Mar 17, 2022 Issued
Array ( [id] => 17708263 [patent_doc_number] => 20220208271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => OPERATING METHOD OF MEMORY SYSTEM INCLUDING MEMORY CONTROLLER AND NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/698056 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698056 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/698056
Operating method of memory system including memory controller and nonvolatile memory device Mar 17, 2022 Issued
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