Search

Nishath Yasmeen

Examiner (ID: 7674, Phone: (571)270-7564 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
561
Issued Applications
400
Pending Applications
60
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19696463 [patent_doc_number] => 20250015008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => DIE EMBEDDED PACKAGE AND METHOD OF FORMING A DIE EMBEDDED PACKAGE [patent_app_type] => utility [patent_app_number] => 18/764578 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764578 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/764578
DIE EMBEDDED PACKAGE AND METHOD OF FORMING A DIE EMBEDDED PACKAGE Jul 4, 2024 Pending
Array ( [id] => 20004617 [patent_doc_number] => 20250142839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => MICROELECTRONIC DEVICES, MEMORY DEVICES, AND METHODS OF FORMING MICROELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/760921 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760921 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760921
MICROELECTRONIC DEVICES, MEMORY DEVICES, AND METHODS OF FORMING MICROELECTRONIC DEVICES Jun 30, 2024 Pending
Array ( [id] => 19515802 [patent_doc_number] => 20240347488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => CHIP STRUCTURE WITH CONDUCTIVE LAYER [patent_app_type] => utility [patent_app_number] => 18/753052 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753052 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753052
Chip structure with conductive layer Jun 24, 2024 Issued
Array ( [id] => 19484080 [patent_doc_number] => 20240332122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => POWER MODULE AND FABRICATION METHOD OF THE SAME, GRAPHITE PLATE, AND POWER SUPPLY EQUIPMENT [patent_app_type] => utility [patent_app_number] => 18/739101 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 57855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739101 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739101
POWER MODULE AND FABRICATION METHOD OF THE SAME, GRAPHITE PLATE, AND POWER SUPPLY EQUIPMENT Jun 9, 2024 Abandoned
Array ( [id] => 20286074 [patent_doc_number] => 20250311316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SILICON CARBIDE POWER DEVICE AND MANUFACTURING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/679389 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18679389 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/679389
SILICON CARBIDE POWER DEVICE AND MANUFACTURING METHOD OF THE SAME May 29, 2024 Pending
Array ( [id] => 20435050 [patent_doc_number] => 12506107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Electronic device and display device using the same [patent_app_type] => utility [patent_app_number] => 18/674681 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 6983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674681 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/674681
Electronic device and display device using the same May 23, 2024 Issued
Array ( [id] => 20183887 [patent_doc_number] => 20250267845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => RECESS GATE AND INTERCONNECTOR STRUCTURE AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 18/635343 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635343 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635343
RECESS GATE AND INTERCONNECTOR STRUCTURE AND METHOD FOR PREPARING THE SAME Apr 14, 2024 Pending
Array ( [id] => 20119610 [patent_doc_number] => 12369348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Fin Field-Effect Transistor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 18/630549 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 5741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630549
Fin Field-Effect Transistor device and method of forming the same Apr 8, 2024 Issued
Array ( [id] => 20291346 [patent_doc_number] => 20250316589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => VERTICAL ANTI-FUSE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/627536 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627536 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/627536
VERTICAL ANTI-FUSE STRUCTURE Apr 4, 2024 Pending
Array ( [id] => 20134081 [patent_doc_number] => 12376412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Semiconductor apparatus and equipment [patent_app_type] => utility [patent_app_number] => 18/626145 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 10674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626145 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626145
Semiconductor apparatus and equipment Apr 2, 2024 Issued
Array ( [id] => 20096280 [patent_doc_number] => 20250226216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => METALLIZATION STRUCTURE FOR COUPLING BOILING ENHANCED LAYER TO SUBSTRATE IN A COOLING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/624906 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624906 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624906
METALLIZATION STRUCTURE FOR COUPLING BOILING ENHANCED LAYER TO SUBSTRATE IN A COOLING SYSTEM Apr 1, 2024 Pending
Array ( [id] => 19288194 [patent_doc_number] => 20240224677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DISPLAY SUBSTRATE AND DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/609424 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609424 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609424
Display substrate and display apparatus Mar 18, 2024 Issued
Array ( [id] => 20183879 [patent_doc_number] => 20250267837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => RECESS GATE AND INTERCONNECTOR STRUCTURE AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 18/604812 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604812 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604812
RECESS GATE AND INTERCONNECTOR STRUCTURE AND METHOD FOR PREPARING THE SAME Mar 13, 2024 Pending
Array ( [id] => 20183886 [patent_doc_number] => 20250267844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => RECESS GATE AND INTERCONNECTOR STRUCTURE AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 18/599255 [patent_app_country] => US [patent_app_date] => 2024-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599255 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/599255
RECESS GATE AND INTERCONNECTOR STRUCTURE AND METHOD FOR PREPARING THE SAME Mar 7, 2024 Pending
Array ( [id] => 20223004 [patent_doc_number] => 20250285935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => ELECTRONIC DEVICE WITH WARPAGE MITIGATION AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/598009 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598009 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598009
ELECTRONIC DEVICE WITH WARPAGE MITIGATION AND METHOD THEREFOR Mar 6, 2024 Pending
Array ( [id] => 19308740 [patent_doc_number] => 20240237323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => WELL PICK-UP REGION DESIGN FOR IMPROVING MEMORY MACRO PERFORMANCE [patent_app_type] => utility [patent_app_number] => 18/444889 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444889 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444889
Well pick-up region design for improving memory macro performance Feb 18, 2024 Issued
Array ( [id] => 20182375 [patent_doc_number] => 20250266333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => SEMICONDUCTOR PACKAGE HAVING PARTIALLY PLATED LEAD FLANK AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/443842 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443842 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443842
SEMICONDUCTOR PACKAGE HAVING PARTIALLY PLATED LEAD FLANK AND METHOD OF MAKING THE SAME Feb 15, 2024 Pending
Array ( [id] => 20182346 [patent_doc_number] => 20250266304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => Semiconductor Wafer with Process Control Monitor Structures [patent_app_type] => utility [patent_app_number] => 18/443886 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443886 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443886
Semiconductor Wafer with Process Control Monitor Structures Feb 15, 2024 Pending
Array ( [id] => 20183885 [patent_doc_number] => 20250267843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => RECESS GATE AND INTERCONNECTOR STRUCTURE AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 18/443733 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443733 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443733
RECESS GATE AND INTERCONNECTOR STRUCTURE AND METHOD FOR PREPARING THE SAME Feb 15, 2024 Pending
Array ( [id] => 19741192 [patent_doc_number] => 12218037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-04 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/441507 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9061 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441507 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441507
Semiconductor device Feb 13, 2024 Issued
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