Search

Nishath Yasmeen

Examiner (ID: 15422, Phone: (571)270-7564 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
537
Issued Applications
389
Pending Applications
48
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13500027 [patent_doc_number] => 20180301556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => VERTICAL TRANSISTORS WITH SIDEWALL GATE AIR GAPS AND METHODS THEREFOR [patent_app_type] => utility [patent_app_number] => 16/016219 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16016219 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/016219
Vertical transistors with sidewall gate air gaps and methods therefor Jun 21, 2018 Issued
Array ( [id] => 14446387 [patent_doc_number] => 20190181067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/001181 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001181 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001181
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME Jun 5, 2018 Abandoned
Array ( [id] => 16928360 [patent_doc_number] => 11049851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Method and system for selectively illuminated integrated photodetectors with configured launching and adaptive junction profile for bandwidth improvement [patent_app_type] => utility [patent_app_number] => 16/001135 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001135 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001135
Method and system for selectively illuminated integrated photodetectors with configured launching and adaptive junction profile for bandwidth improvement Jun 5, 2018 Issued
Array ( [id] => 15260121 [patent_doc_number] => 20190378794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => BANDGAP REFERENCE DIODE USING THIN FILM TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/001083 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001083 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001083
BANDGAP REFERENCE DIODE USING THIN FILM TRANSISTORS Jun 5, 2018 Abandoned
Array ( [id] => 15154331 [patent_doc_number] => 20190355643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => Wire Bonded Package with Single Piece Exposed Heat Slug and Leads [patent_app_type] => utility [patent_app_number] => 15/983621 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983621 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/983621
Wire bonded package with single piece exposed heat slug and leads May 17, 2018 Issued
Array ( [id] => 15286467 [patent_doc_number] => 10515903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Selective CVD alignment-mark topography assist for non-volatile memory [patent_app_type] => utility [patent_app_number] => 15/983689 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6605 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983689 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/983689
Selective CVD alignment-mark topography assist for non-volatile memory May 17, 2018 Issued
Array ( [id] => 16048061 [patent_doc_number] => 10685914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/983682 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 43 [patent_no_of_words] => 12005 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/983682
Semiconductor device and manufacturing method thereof May 17, 2018 Issued
Array ( [id] => 15791741 [patent_doc_number] => 10629602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Static random access memory cells with arranged vertical-transport field-effect transistors [patent_app_type] => utility [patent_app_number] => 15/983627 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5386 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15983627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/983627
Static random access memory cells with arranged vertical-transport field-effect transistors May 17, 2018 Issued
Array ( [id] => 13832533 [patent_doc_number] => 20190019751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => FUSE FABRICATION METHOD [patent_app_type] => utility [patent_app_number] => 15/978153 [patent_app_country] => US [patent_app_date] => 2018-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3502 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15978153 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/978153
FUSE FABRICATION METHOD May 12, 2018 Abandoned
Array ( [id] => 15123459 [patent_doc_number] => 20190348363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => SEMICONDUCTOR DEVICES HAVING ELECTROSTATIC DISCHARGE LAYOUTS FOR REDUCED CAPACITANCE [patent_app_type] => utility [patent_app_number] => 15/976674 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976674 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976674
Semiconductor devices having electrostatic discharge layouts for reduced capacitance May 9, 2018 Issued
Array ( [id] => 13629781 [patent_doc_number] => 20180366443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => FINER GRAIN DYNAMIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 15/976580 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976580 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976580
Finer grain dynamic random access memory May 9, 2018 Issued
Array ( [id] => 15123479 [patent_doc_number] => 20190348373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => Semiconductor Device with Stress Relieving Structure [patent_app_type] => utility [patent_app_number] => 15/976653 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976653 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976653
Semiconductor Device with Stress Relieving Structure May 9, 2018 Abandoned
Array ( [id] => 15123471 [patent_doc_number] => 20190348369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => METHOD AND APPARATUS FOR PROTECTING METAL INTERCONNECT FROM HALOGEN BASED PRECURSORS [patent_app_type] => utility [patent_app_number] => 15/976507 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976507
METHOD AND APPARATUS FOR PROTECTING METAL INTERCONNECT FROM HALOGEN BASED PRECURSORS May 9, 2018 Abandoned
Array ( [id] => 15123787 [patent_doc_number] => 20190348527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => Fin and Gate Dimensions for Optimizing Gate Formation [patent_app_type] => utility [patent_app_number] => 15/976664 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976664 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976664
Fin and gate dimensions for optimizing gate formation May 9, 2018 Issued
Array ( [id] => 15045733 [patent_doc_number] => 20190333871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => MIXING ORGANIC MATERIALS INTO HYBRID PACKAGES [patent_app_type] => utility [patent_app_number] => 15/966630 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966630 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966630
Mixing organic materials into hybrid packages Apr 29, 2018 Issued
Array ( [id] => 15611387 [patent_doc_number] => 10586763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Semiconductor device and method of manufacture [patent_app_type] => utility [patent_app_number] => 15/966558 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966558 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966558
Semiconductor device and method of manufacture Apr 29, 2018 Issued
Array ( [id] => 16631668 [patent_doc_number] => 20210050321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE USING NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 16/969357 [patent_app_country] => US [patent_app_date] => 2018-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16969357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/969357
Noble metal-coated silver wire for ball bonding and method for producing the same, and semiconductor device using noble metal-coated silver wire for ball bonding and method for producing the same Apr 18, 2018 Issued
Array ( [id] => 15218145 [patent_doc_number] => 20190371759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => PHYSICAL QUANTITY MEASUREMENT DEVICE AND METHOD FOR MANUFACTURING SAME, AND PHYSICAL QUANTITY MEASUREMENT ELEMENT [patent_app_type] => utility [patent_app_number] => 16/477766 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16477766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/477766
PHYSICAL QUANTITY MEASUREMENT DEVICE AND METHOD FOR MANUFACTURING SAME, AND PHYSICAL QUANTITY MEASUREMENT ELEMENT Jan 23, 2018 Abandoned
Array ( [id] => 16677391 [patent_doc_number] => 20210066157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => POWER ELECTRONICS MODULE AND A METHOD OF PRODUCING A POWER ELECTRONICS MODULE [patent_app_type] => utility [patent_app_number] => 16/963357 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16963357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/963357
POWER ELECTRONICS MODULE AND A METHOD OF PRODUCING A POWER ELECTRONICS MODULE Jan 17, 2018 Abandoned
Array ( [id] => 14769213 [patent_doc_number] => 10396008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/855210 [patent_app_country] => US [patent_app_date] => 2017-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 8495 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15855210 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/855210
Semiconductor device Dec 26, 2017 Issued
Menu