Search

Nishath Yasmeen

Examiner (ID: 2886, Phone: (571)270-7564 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
545
Issued Applications
390
Pending Applications
55
Abandoned Applications
114

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13201799 [patent_doc_number] => 10115820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Vertical transistors with sidewall gate air gaps and methods therefor [patent_app_type] => utility [patent_app_number] => 15/370193 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 50 [patent_no_of_words] => 12290 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370193 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/370193
Vertical transistors with sidewall gate air gaps and methods therefor Dec 5, 2016 Issued
Array ( [id] => 12027115 [patent_doc_number] => 20170317214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/370182 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 10162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370182 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/370182
SEMICONDUCTOR DEVICE Dec 5, 2016 Abandoned
Array ( [id] => 12127792 [patent_doc_number] => 20180011378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'LIQUID CRYSTAL DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/370227 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13202 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370227 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/370227
Liquid crystal display device Dec 5, 2016 Issued
Array ( [id] => 15015725 [patent_doc_number] => 10454026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Controlling dopant concentration in correlated electron materials [patent_app_type] => utility [patent_app_number] => 15/370168 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 11843 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370168 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/370168
Controlling dopant concentration in correlated electron materials Dec 5, 2016 Issued
Array ( [id] => 11517757 [patent_doc_number] => 20170084831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'VERTICAL HALL EFFECT ELEMENT WITH IMPROVED SENSITIVITY' [patent_app_type] => utility [patent_app_number] => 15/370107 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5947 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370107 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/370107
Vertical hall effect element with improved sensitivity Dec 5, 2016 Issued
Array ( [id] => 13201731 [patent_doc_number] => 10115786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Capacitor and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/352551 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2410 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15352551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/352551
Capacitor and method for fabricating the same Nov 14, 2016 Issued
Array ( [id] => 11862130 [patent_doc_number] => 09741823 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-22 [patent_title] => 'Fin cut during replacement gate formation' [patent_app_type] => utility [patent_app_number] => 15/336886 [patent_app_country] => US [patent_app_date] => 2016-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 29 [patent_no_of_words] => 9388 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15336886 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/336886
Fin cut during replacement gate formation Oct 27, 2016 Issued
Array ( [id] => 11446413 [patent_doc_number] => 20170047433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/335885 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 19239 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15335885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/335885
Semiconductor device and method of fabricating the same Oct 26, 2016 Issued
Array ( [id] => 12147575 [patent_doc_number] => 09881833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-30 [patent_title] => 'Barrier planarization for interconnect metallization' [patent_app_type] => utility [patent_app_number] => 15/334796 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4991 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15334796 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/334796
Barrier planarization for interconnect metallization Oct 25, 2016 Issued
Array ( [id] => 12202441 [patent_doc_number] => 09905513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'Selective blocking boundary placement for circuit locations requiring electromigration short-length' [patent_app_type] => utility [patent_app_number] => 15/332194 [patent_app_country] => US [patent_app_date] => 2016-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 7137 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15332194 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/332194
Selective blocking boundary placement for circuit locations requiring electromigration short-length Oct 23, 2016 Issued
Array ( [id] => 12229811 [patent_doc_number] => 09917060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-13 [patent_title] => 'Forming a contact for a semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/331331 [patent_app_country] => US [patent_app_date] => 2016-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 5746 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15331331 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/331331
Forming a contact for a semiconductor device Oct 20, 2016 Issued
Array ( [id] => 13755049 [patent_doc_number] => 10170478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Spacer for dual epi CMOS devices [patent_app_type] => utility [patent_app_number] => 15/297730 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 92 [patent_no_of_words] => 6266 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297730 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297730
Spacer for dual epi CMOS devices Oct 18, 2016 Issued
Array ( [id] => 13132037 [patent_doc_number] => 10083958 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Deep trench metal-insulator-metal capacitors [patent_app_type] => utility [patent_app_number] => 15/292488 [patent_app_country] => US [patent_app_date] => 2016-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3134 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15292488 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/292488
Deep trench metal-insulator-metal capacitors Oct 12, 2016 Issued
Array ( [id] => 12019783 [patent_doc_number] => 09812494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Methods and apparatus for improving micro-LED devices' [patent_app_type] => utility [patent_app_number] => 15/284369 [patent_app_country] => US [patent_app_date] => 2016-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4826 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15284369 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/284369
Methods and apparatus for improving micro-LED devices Oct 2, 2016 Issued
Array ( [id] => 12263767 [patent_doc_number] => 20180082963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/271748 [patent_app_country] => US [patent_app_date] => 2016-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 8897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15271748 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/271748
Semiconductor structure and manufacturing method thereof Sep 20, 2016 Issued
Array ( [id] => 12263771 [patent_doc_number] => 20180082967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/271603 [patent_app_country] => US [patent_app_date] => 2016-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 6983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15271603 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/271603
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF Sep 20, 2016 Abandoned
Array ( [id] => 11517390 [patent_doc_number] => 20170084464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'GERMANIUM-CONTAINING SEMICONDUCTOR DEVICE AND METHOD OF FORMING' [patent_app_type] => utility [patent_app_number] => 15/267890 [patent_app_country] => US [patent_app_date] => 2016-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15267890 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/267890
GERMANIUM-CONTAINING SEMICONDUCTOR DEVICE AND METHOD OF FORMING Sep 15, 2016 Abandoned
Array ( [id] => 14205611 [patent_doc_number] => 10269933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Recessing STI to increase Fin height in Fin-first process [patent_app_type] => utility [patent_app_number] => 15/253977 [patent_app_country] => US [patent_app_date] => 2016-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 32 [patent_no_of_words] => 7542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15253977 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/253977
Recessing STI to increase Fin height in Fin-first process Aug 31, 2016 Issued
Array ( [id] => 12223389 [patent_doc_number] => 20180061749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'POST ZERO VIA LAYER KEEP OUT ZONE OVER THROUGH SILICON VIA REDUCING BEOL PUMPING EFFECTS' [patent_app_type] => utility [patent_app_number] => 15/249700 [patent_app_country] => US [patent_app_date] => 2016-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3639 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15249700 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/249700
Post zero via layer keep out zone over through silicon via reducing BEOL pumping effects Aug 28, 2016 Issued
Array ( [id] => 12054496 [patent_doc_number] => 20170330841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'Floating Die Package' [patent_app_type] => utility [patent_app_number] => 15/248151 [patent_app_country] => US [patent_app_date] => 2016-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6896 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15248151 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/248151
Floating die package Aug 25, 2016 Issued
Menu