Nitin Parekh

Array ( [id] => 16425033 [patent_doc_number] => 20200350231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => RESERVOIR STRUCTURE AND SYSTEM FORMING GAP FOR LIQUID THERMAL INTERFACE MATERIAL [patent_app_type] => utility [patent_app_number] => 16/837777 [patent_app_country] => US [patent_app_date] => 2020-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16837777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16609321 [patent_doc_number] => 10910335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Semiconductor device and a method of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 16/836441 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 11978 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17615320 [patent_doc_number] => 20220157600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => FILM FORMING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, FILM FORMING DEVICE, AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/594029 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10685 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17594029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16180375 [patent_doc_number] => 20200227344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SEMICONDUCTOR PACKAGE SUBSTRATE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 16/829793 [patent_app_country] => US [patent_app_date] => 2020-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16829793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17862843 [patent_doc_number] => 11444004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Cooler [patent_app_type] => utility [patent_app_number] => 16/806490 [patent_app_country] => US [patent_app_date] => 2020-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6778 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16806490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17737945 [patent_doc_number] => 20220223407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => METHOD AND DEVICE FOR FORMING GRAPHENE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/593220 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17593220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19277321 [patent_doc_number] => 12027453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Embedded semiconductor packages and methods thereof [patent_app_type] => utility [patent_app_number] => 17/433801 [patent_app_country] => US [patent_app_date] => 2020-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 11611 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17433801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16080791 [patent_doc_number] => 20200194382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => SEMICONDUCTOR PACKAGE WITH IN-PACKAGE COMPARTMENTAL SHIELDING AND IMPROVED HEAT-DISSIPATION PERFORMANCE [patent_app_type] => utility [patent_app_number] => 16/798449 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16798449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18014722 [patent_doc_number] => 11507017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Package aspect of heat-dissipating lid and reservoir structure for liquid thermal interfacing materials [patent_app_type] => utility [patent_app_number] => 16/794652 [patent_app_country] => US [patent_app_date] => 2020-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 7236 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16794652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19277523 [patent_doc_number] => 12027656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Optoelectronic semiconductor component and method for producing optoelectronic semiconductor components [patent_app_type] => utility [patent_app_number] => 17/431073 [patent_app_country] => US [patent_app_date] => 2020-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 7787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17431073 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16025029 [patent_doc_number] => 20200187358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => METHOD FOR MANUFACTURING AN ELECTRONIC MODULE AND ELECTRONIC MODULE [patent_app_type] => utility [patent_app_number] => 16/788701 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17025467 [patent_doc_number] => 20210249339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => PACKAGE STRUCTURES [patent_app_type] => utility [patent_app_number] => 16/786139 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16425030 [patent_doc_number] => 20200350228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => HEAT SINK ASPECT OF HEAT DISSIPATING LID AND RESERVOIR STRUCTURE FLIP CHIP PACKAGE FOR LIQUID THERMAL INTERFACING MATERIALS [patent_app_type] => utility [patent_app_number] => 16/785577 [patent_app_country] => US [patent_app_date] => 2020-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17193000 [patent_doc_number] => 11161737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Method for forming hermetic seals in MEMS devices [patent_app_type] => utility [patent_app_number] => 16/773042 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16773042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16440423 [patent_doc_number] => 20200357750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => PACKAGE STRUCTURE AND FABRICATION METHODS [patent_app_type] => utility [patent_app_number] => 16/746711 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17239545 [patent_doc_number] => 11183436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Power module package and packaging techniques [patent_app_type] => utility [patent_app_number] => 16/746275 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4590 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15906177 [patent_doc_number] => 20200152609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => METHOD THEREOF OF PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/741749 [patent_app_country] => US [patent_app_date] => 2020-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16936514 [patent_doc_number] => 20210202403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => ELECTROSTATIC DISCHARGE PROTECTION IN INTEGRATED CIRCUITS USING MATERIALS WITH OPTICALLY CONTROLLED ELECTRICAL CONDUCTIVITY [patent_app_type] => utility [patent_app_number] => 16/728127 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15877577 [patent_doc_number] => 20200146192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => SEMICONDUCTOR ASSEMBLY HAVING DUAL WIRING STRUCTURES AND WARP BALANCER [patent_app_type] => utility [patent_app_number] => 16/727661 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16920494 [patent_doc_number] => 20210193586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => CRYPTOGRAPHIC SYSTEM-IN-PACKAGE (CSIP) [patent_app_type] => utility [patent_app_number] => 16/718586 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718586 [rel_patent_id] =>[rel_patent_doc_number] =>)