
Nitin Parekh
Examiner (ID: 329, Phone: (571)272-1663 , Office: P/2811 )
| Most Active Art Unit | 2811 |
| Art Unit(s) | 2811 |
| Total Applications | 1975 |
| Issued Applications | 1684 |
| Pending Applications | 28 |
| Abandoned Applications | 273 |
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