Search

Nitin Parekh

Examiner (ID: 2427, Phone: (571)272-1663 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
1977
Issued Applications
1684
Pending Applications
30
Abandoned Applications
273

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15807569 [patent_doc_number] => 20200126927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => SEMICONDUCTOR CHIP INCLUDING ALIGNMENT PATTERN [patent_app_type] => utility [patent_app_number] => 16/430630 [patent_app_country] => US [patent_app_date] => 2019-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430630 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430630
Semiconductor chip including alignment pattern Jun 3, 2019 Issued
Array ( [id] => 16487729 [patent_doc_number] => 20200381338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/430260 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3568 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430260 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430260
SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME Jun 2, 2019 Abandoned
Array ( [id] => 17878582 [patent_doc_number] => 11450606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Chip scale package structure and method of forming the same [patent_app_type] => utility [patent_app_number] => 16/430076 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 7698 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430076 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430076
Chip scale package structure and method of forming the same Jun 2, 2019 Issued
Array ( [id] => 14904339 [patent_doc_number] => 20190295935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => Flat No-Lead Packages with Electroplated Edges [patent_app_type] => utility [patent_app_number] => 16/427172 [patent_app_country] => US [patent_app_date] => 2019-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427172 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/427172
Flat no-lead packages with electroplated edges May 29, 2019 Issued
Array ( [id] => 19356904 [patent_doc_number] => 12057361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Chip encapsulation structure and encapsulation method [patent_app_type] => utility [patent_app_number] => 17/614434 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6387 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17614434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/614434
Chip encapsulation structure and encapsulation method May 27, 2019 Issued
Array ( [id] => 17638120 [patent_doc_number] => 11348854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Semiconductor package structure and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/415993 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 42 [patent_no_of_words] => 10052 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16415993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/415993
Semiconductor package structure and method for manufacturing the same May 16, 2019 Issued
Array ( [id] => 18358088 [patent_doc_number] => 11646498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Package integrated cavity resonator antenna [patent_app_type] => utility [patent_app_number] => 16/414356 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 13475 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414356
Package integrated cavity resonator antenna May 15, 2019 Issued
Array ( [id] => 16356463 [patent_doc_number] => 10796981 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-06 [patent_title] => Chip to lead interconnect in encapsulant of molded semiconductor package [patent_app_type] => utility [patent_app_number] => 16/413059 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 9880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/413059
Chip to lead interconnect in encapsulant of molded semiconductor package May 14, 2019 Issued
Array ( [id] => 14784819 [patent_doc_number] => 20190267307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => HEAT CONDUCTIVE WIRING BOARD AND SEMICONDUCTOR ASSEMBLY USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/411949 [patent_app_country] => US [patent_app_date] => 2019-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16411949 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/411949
HEAT CONDUCTIVE WIRING BOARD AND SEMICONDUCTOR ASSEMBLY USING THE SAME May 13, 2019 Abandoned
Array ( [id] => 15857255 [patent_doc_number] => 10643924 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-05-05 [patent_title] => Heat-dissipating lid with reservoir structure and associated lidded flip chip package allowing for liquid thermal interfacing materials [patent_app_type] => utility [patent_app_number] => 16/400666 [patent_app_country] => US [patent_app_date] => 2019-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 7239 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16400666 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/400666
Heat-dissipating lid with reservoir structure and associated lidded flip chip package allowing for liquid thermal interfacing materials Apr 30, 2019 Issued
Array ( [id] => 14812917 [patent_doc_number] => 20190273068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => 3D Package Structure and Methods of Forming Same [patent_app_type] => utility [patent_app_number] => 16/397479 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16397479 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/397479
3D package structure and methods of forming same Apr 28, 2019 Issued
Array ( [id] => 16668433 [patent_doc_number] => 10937688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Semiconductor package and method of fabricating semiconductor package [patent_app_type] => utility [patent_app_number] => 16/396793 [patent_app_country] => US [patent_app_date] => 2019-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 6808 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16396793 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/396793
Semiconductor package and method of fabricating semiconductor package Apr 28, 2019 Issued
Array ( [id] => 16356500 [patent_doc_number] => 10797018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages [patent_app_type] => utility [patent_app_number] => 16/392221 [patent_app_country] => US [patent_app_date] => 2019-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4832 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16392221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/392221
Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages Apr 22, 2019 Issued
Array ( [id] => 16301054 [patent_doc_number] => 20200286777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 16/389644 [patent_app_country] => US [patent_app_date] => 2019-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8714 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16389644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/389644
INTERCONNECT STRUCTURE AND METHOD FOR PREPARING THE SAME Apr 18, 2019 Abandoned
Array ( [id] => 18704711 [patent_doc_number] => 11791228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Method for forming embedded grounding planes on interconnect layers [patent_app_type] => utility [patent_app_number] => 16/380486 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 7386 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380486 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380486
Method for forming embedded grounding planes on interconnect layers Apr 9, 2019 Issued
Array ( [id] => 15969611 [patent_doc_number] => 20200168557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/379805 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9119 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16379805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/379805
SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF Apr 9, 2019 Abandoned
Array ( [id] => 16819766 [patent_doc_number] => 11004603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Vertical electrode decoupling/bypass capacitor [patent_app_type] => utility [patent_app_number] => 16/357516 [patent_app_country] => US [patent_app_date] => 2019-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 11991 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16357516 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/357516
Vertical electrode decoupling/bypass capacitor Mar 18, 2019 Issued
Array ( [id] => 14876265 [patent_doc_number] => 20190288374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => ANTENNA FEEDER PACKAGE STRUCTURE AND PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 16/354477 [patent_app_country] => US [patent_app_date] => 2019-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16354477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/354477
Antenna feeder package structure and packaging method Mar 14, 2019 Issued
Array ( [id] => 16316183 [patent_doc_number] => 20200294921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/354135 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16354135 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/354135
Package structure and method of manufacturing the same Mar 13, 2019 Issued
Array ( [id] => 16316383 [patent_doc_number] => 20200295121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/354142 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16354142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/354142
Package and manufacturing method thereof Mar 13, 2019 Issued
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