Search

Nitin Parekh

Examiner (ID: 329, Phone: (571)272-1663 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
1975
Issued Applications
1684
Pending Applications
28
Abandoned Applications
273

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17599414 [patent_doc_number] => 20220148988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => MERGED POWER PAD FOR IMPROVING INTEGRATED CIRCUIT POWER DELIVERY [patent_app_type] => utility [patent_app_number] => 17/580961 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580961 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580961
Merged power pad for improving integrated circuit power delivery Jan 20, 2022 Issued
Array ( [id] => 19505104 [patent_doc_number] => 12116516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Metallic structure for optical semiconductor device, method for producing the same, and optical semiconductor device using the same [patent_app_type] => utility [patent_app_number] => 17/576221 [patent_app_country] => US [patent_app_date] => 2022-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11830 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17576221 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/576221
Metallic structure for optical semiconductor device, method for producing the same, and optical semiconductor device using the same Jan 13, 2022 Issued
Array ( [id] => 19720333 [patent_doc_number] => 12205876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Embedded packaging structure, preparation method thereof, and terminal device [patent_app_type] => utility [patent_app_number] => 17/570889 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 9949 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17570889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/570889
Embedded packaging structure, preparation method thereof, and terminal device Jan 6, 2022 Issued
Array ( [id] => 19858252 [patent_doc_number] => 12261103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/647144 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 12247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17647144 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/647144
Semiconductor package Jan 4, 2022 Issued
Array ( [id] => 18857449 [patent_doc_number] => 11855045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Semiconductor device with discrete blocks [patent_app_type] => utility [patent_app_number] => 17/567435 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567435 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/567435
Semiconductor device with discrete blocks Jan 2, 2022 Issued
Array ( [id] => 18456398 [patent_doc_number] => 20230197680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => INTEGRATED ANTENNA PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/564197 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564197
Integrated antenna package structure Dec 27, 2021 Issued
Array ( [id] => 17723379 [patent_doc_number] => 20220216101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => LINER AND BARRIER LAYER IN DUAL DAMASCENE CU INTERCONNECT FOR ENHANCED EM AND PROCESS [patent_app_type] => utility [patent_app_number] => 17/563347 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563347 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563347
Liner and barrier layer in dual damascene cu interconnect for enhanced EM and process Dec 27, 2021 Issued
Array ( [id] => 18482638 [patent_doc_number] => 11696407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Core layer with fully encapsulated co-axial magnetic material around PTH in IC package substrate [patent_app_type] => utility [patent_app_number] => 17/560004 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5794 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560004 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560004
Core layer with fully encapsulated co-axial magnetic material around PTH in IC package substrate Dec 21, 2021 Issued
Array ( [id] => 19376648 [patent_doc_number] => 12068228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Leadless semiconductor package with shielded die-to-pad contacts [patent_app_type] => utility [patent_app_number] => 17/551366 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5515 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551366 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551366
Leadless semiconductor package with shielded die-to-pad contacts Dec 14, 2021 Issued
Array ( [id] => 17780158 [patent_doc_number] => 20220246508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => BALL PAD DESIGN FOR SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 17/547127 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17547127 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/547127
Ball pad design for semiconductor packages Dec 8, 2021 Issued
Array ( [id] => 17708678 [patent_doc_number] => 20220208686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => Semiconductor Device and Method of Forming Leadframe with Clip Bond for Electrical Interconnect [patent_app_type] => utility [patent_app_number] => 17/643244 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643244 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643244
Semiconductor device and method of forming leadframe with clip bond for electrical interconnect Dec 7, 2021 Issued
Array ( [id] => 17660822 [patent_doc_number] => 20220181287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/537792 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/537792
Semiconductor device Nov 29, 2021 Issued
Array ( [id] => 18608134 [patent_doc_number] => 11749612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Semiconductor package device [patent_app_type] => utility [patent_app_number] => 17/536158 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5556 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536158 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536158
Semiconductor package device Nov 28, 2021 Issued
Array ( [id] => 17645265 [patent_doc_number] => 20220173004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => Semiconductor Packaging Method, Semiconductor Assembly and Electronic Device Comprising Semiconductor Assembly [patent_app_type] => utility [patent_app_number] => 17/535983 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535983 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535983
Semiconductor packaging method, semiconductor assembly and electronic device comprising semiconductor assembly Nov 25, 2021 Issued
Array ( [id] => 19858255 [patent_doc_number] => 12261106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/535093 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 13332 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535093
Semiconductor package Nov 23, 2021 Issued
Array ( [id] => 18024330 [patent_doc_number] => 20220375829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/533606 [patent_app_country] => US [patent_app_date] => 2021-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17533606 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/533606
Semiconductor package Nov 22, 2021 Issued
Array ( [id] => 17599419 [patent_doc_number] => 20220148993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/524720 [patent_app_country] => US [patent_app_date] => 2021-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524720 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524720
Semiconductor package and method for manufacturing the same Nov 10, 2021 Issued
Array ( [id] => 17402920 [patent_doc_number] => 20220045011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SEMICONDUCTOR DEVICES WITH BACKSIDE POWER DISTRIBUTION NETWORK AND FRONTSIDE THROUGH SILICON VIA [patent_app_type] => utility [patent_app_number] => 17/452188 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452188 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452188
Semiconductor devices with backside power distribution network and frontside through silicon via Oct 24, 2021 Issued
Array ( [id] => 19597032 [patent_doc_number] => 12154886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Semiconductor packages including electrical redistribution layers of different thicknesses and methods for manufacturing thereof [patent_app_type] => utility [patent_app_number] => 17/502163 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 28 [patent_no_of_words] => 7870 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502163 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502163
Semiconductor packages including electrical redistribution layers of different thicknesses and methods for manufacturing thereof Oct 14, 2021 Issued
Array ( [id] => 17373698 [patent_doc_number] => 20220028750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => ELECTRONIC COMPONENT MODULE [patent_app_type] => utility [patent_app_number] => 17/498389 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498389 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498389
Electronic component module Oct 10, 2021 Issued
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