Nitin Parekh

Array ( [id] => 17463764 [patent_doc_number] => 20220077070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => STACKED SEMICONDUCTOR PACKAGE WITH FLYOVER BRIDGE [patent_app_type] => utility [patent_app_number] => 17/090933 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17559135 [patent_doc_number] => 11315857 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Package structures [patent_app_type] => utility [patent_app_number] => 17/081546 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17623211 [patent_doc_number] => 11342275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Leadless power amplifier packages including topside terminations and methods for the fabrication thereof [patent_app_type] => utility [patent_app_number] => 17/077583 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 15401 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16617753 [patent_doc_number] => 20210036406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => ANTENNA PACKAGE STRUCTURE AND ANTENNA PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 17/076672 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18219571 [patent_doc_number] => 11594520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Semiconductor package for thermal dissipation [patent_app_type] => utility [patent_app_number] => 17/073953 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073953 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16631629 [patent_doc_number] => 20210050282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUFACTURING [patent_app_type] => utility [patent_app_number] => 17/073190 [patent_app_country] => US [patent_app_date] => 2020-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16850614 [patent_doc_number] => 20210151359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => Semiconductor Device and Method of Forming Mold Degating Structure for Pre-Molded Substrate [patent_app_type] => utility [patent_app_number] => 17/067277 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17878590 [patent_doc_number] => 11450614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 17/035000 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16765502 [patent_doc_number] => 20210111084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => STACKED CIRCUIT PACKAGE WITH MOLDED BASE HAVING LASER DRILLED OPENINGS FOR UPPER PACKAGE [patent_app_type] => utility [patent_app_number] => 17/033245 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17486031 [patent_doc_number] => 20220093535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => ELECTRONIC SUBSTRATES HAVING EMBEDDED INDUCTORS [patent_app_type] => utility [patent_app_number] => 17/029866 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17029866 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17908667 [patent_doc_number] => 11462530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Multi-stack package-on-package structures [patent_app_type] => utility [patent_app_number] => 17/026825 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17040669 [patent_doc_number] => 20210257305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => SEMICONDUCTOR PACKAGE, AND PACKAGE ON PACKAGE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/024852 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17024852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16536534 [patent_doc_number] => 10879147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Method of manufacturing package structure [patent_app_type] => utility [patent_app_number] => 17/017679 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 8178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18120567 [patent_doc_number] => 11551966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Method of forming semiconductor structure having layer with re-entrant profile [patent_app_type] => utility [patent_app_number] => 17/000122 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 5133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17000122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18562982 [patent_doc_number] => 11728235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor device and method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/997767 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10318 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18562982 [patent_doc_number] => 11728235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor device and method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/997767 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10318 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18562982 [patent_doc_number] => 11728235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor device and method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/997767 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10318 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16677392 [patent_doc_number] => 20210066158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/997622 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18562982 [patent_doc_number] => 11728235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor device and method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 16/997767 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 10318 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16660718 [patent_doc_number] => 20210057355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR DEVICE HAVING CAVITIES AT AN INTERFACE OF AN ENCAPSULANT AND A DIE PAD OR LEADS [patent_app_type] => utility [patent_app_number] => 16/996712 [patent_app_country] => US [patent_app_date] => 2020-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16996712 [rel_patent_id] =>[rel_patent_doc_number] =>)