Nora Maureen Rooney
Examiner (ID: 173, Phone: (571)272-9937 , Office: P/1644 )
Most Active Art Unit | 1644 |
Art Unit(s) | 1641, 1644 |
Total Applications | 861 |
Issued Applications | 413 |
Pending Applications | 100 |
Abandoned Applications | 348 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3891772
[patent_doc_number] => 05798967
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Sensing scheme for non-volatile memories'
[patent_app_type] => 1
[patent_app_number] => 8/801414
[patent_app_country] => US
[patent_app_date] => 1997-02-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/798/05798967.pdf
[firstpage_image] =>[orig_patent_app_number] => 801414
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/801414 | Sensing scheme for non-volatile memories | Feb 21, 1997 | Issued |
Array
(
[id] => 3756724
[patent_doc_number] => 05717633
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Low power consuming memory sense amplifying circuitry'
[patent_app_type] => 1
[patent_app_number] => 8/798816
[patent_app_country] => US
[patent_app_date] => 1997-02-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/717/05717633.pdf
[firstpage_image] =>[orig_patent_app_number] => 798816
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/798816 | Low power consuming memory sense amplifying circuitry | Feb 10, 1997 | Issued |
Array
(
[id] => 3867722
[patent_doc_number] => 05706236
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/797044
[patent_app_country] => US
[patent_app_date] => 1997-02-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/706/05706236.pdf
[firstpage_image] =>[orig_patent_app_number] => 797044
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/797044 | Semiconductor memory device | Feb 9, 1997 | Issued |
Array
(
[id] => 3851858
[patent_doc_number] => 05708604
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Dynamic selection control in a memory'
[patent_app_type] => 1
[patent_app_number] => 8/789616
[patent_app_country] => US
[patent_app_date] => 1997-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/708/05708604.pdf
[firstpage_image] =>[orig_patent_app_number] => 789616
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/789616 | Dynamic selection control in a memory | Jan 26, 1997 | Issued |
Array
(
[id] => 3738390
[patent_doc_number] => 05671173
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Semiconductor integrated circuit device with oblique metallization lines over memory bit and word lines'
[patent_app_type] => 1
[patent_app_number] => 8/789124
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[pdf_file] => patents/05/671/05671173.pdf
[firstpage_image] =>[orig_patent_app_number] => 789124
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/789124 | Semiconductor integrated circuit device with oblique metallization lines over memory bit and word lines | Jan 26, 1997 | Issued |
Array
(
[id] => 3739273
[patent_doc_number] => 05703825
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-30
[patent_title] => 'Semiconductor integrated circuit device having a leakage current reduction means'
[patent_app_type] => 1
[patent_app_number] => 8/785417
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[pdf_file] => patents/05/703/05703825.pdf
[firstpage_image] =>[orig_patent_app_number] => 785417
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/785417 | Semiconductor integrated circuit device having a leakage current reduction means | Jan 22, 1997 | Issued |
Array
(
[id] => 3756579
[patent_doc_number] => 05717625
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/784963
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[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/717/05717625.pdf
[firstpage_image] =>[orig_patent_app_number] => 784963
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/784963 | Semiconductor memory device | Jan 15, 1997 | Issued |
Array
(
[id] => 3830572
[patent_doc_number] => 05790459
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Memory circuit for performing threshold voltage tests on cells of a memory array'
[patent_app_type] => 1
[patent_app_number] => 8/781427
[patent_app_country] => US
[patent_app_date] => 1997-01-10
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/790/05790459.pdf
[firstpage_image] =>[orig_patent_app_number] => 781427
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/781427 | Memory circuit for performing threshold voltage tests on cells of a memory array | Jan 9, 1997 | Issued |
Array
(
[id] => 3866966
[patent_doc_number] => 05768197
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Redundancy circuit for semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/774318
[patent_app_country] => US
[patent_app_date] => 1996-12-24
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[pdf_file] => patents/05/768/05768197.pdf
[firstpage_image] =>[orig_patent_app_number] => 774318
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/774318 | Redundancy circuit for semiconductor memory device | Dec 23, 1996 | Issued |
Array
(
[id] => 3767125
[patent_doc_number] => 05742188
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Universal input data sampling circuit and method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/763123
[patent_app_country] => US
[patent_app_date] => 1996-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/742/05742188.pdf
[firstpage_image] =>[orig_patent_app_number] => 763123
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/763123 | Universal input data sampling circuit and method thereof | Dec 9, 1996 | Issued |
Array
(
[id] => 3671750
[patent_doc_number] => 05657290
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Sense amplifier for reading logic devices'
[patent_app_type] => 1
[patent_app_number] => 8/746179
[patent_app_country] => US
[patent_app_date] => 1996-11-05
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/657/05657290.pdf
[firstpage_image] =>[orig_patent_app_number] => 746179
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/746179 | Sense amplifier for reading logic devices | Nov 4, 1996 | Issued |
Array
(
[id] => 3703140
[patent_doc_number] => 05650957
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-22
[patent_title] => 'Semiconductor memory cell and process for formation thereof'
[patent_app_type] => 1
[patent_app_number] => 8/730256
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[pdf_file] => patents/05/650/05650957.pdf
[firstpage_image] =>[orig_patent_app_number] => 730256
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730256 | Semiconductor memory cell and process for formation thereof | Oct 14, 1996 | Issued |
Array
(
[id] => 3866990
[patent_doc_number] => 05768199
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Semiconductor memory device with dual precharge operations'
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[patent_app_number] => 8/709013
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[pdf_file] => patents/05/768/05768199.pdf
[firstpage_image] =>[orig_patent_app_number] => 709013
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/709013 | Semiconductor memory device with dual precharge operations | Sep 5, 1996 | Issued |
Array
(
[id] => 3836191
[patent_doc_number] => 05732031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Address comparing for non-precharged redundancy address matching with redundancy disable mode'
[patent_app_type] => 1
[patent_app_number] => 8/709162
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[pdf_file] => patents/05/732/05732031.pdf
[firstpage_image] =>[orig_patent_app_number] => 709162
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/709162 | Address comparing for non-precharged redundancy address matching with redundancy disable mode | Sep 5, 1996 | Issued |
Array
(
[id] => 3697266
[patent_doc_number] => 05696723
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Defect relief decision circuit with dual-fused clocked inverter'
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[firstpage_image] =>[orig_patent_app_number] => 705418
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/705418 | Defect relief decision circuit with dual-fused clocked inverter | Aug 28, 1996 | Issued |
Array
(
[id] => 3802341
[patent_doc_number] => 05841698
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Semiconductor device'
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[pdf_file] => patents/05/841/05841698.pdf
[firstpage_image] =>[orig_patent_app_number] => 697511
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/697511 | Semiconductor device | Aug 25, 1996 | Issued |
Array
(
[id] => 3736386
[patent_doc_number] => 05652719
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[patent_issue_date] => 1997-07-29
[patent_title] => 'Nonvolatile semiconductor memory device'
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[firstpage_image] =>[orig_patent_app_number] => 682009
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/682009 | Nonvolatile semiconductor memory device | Jul 15, 1996 | Issued |
Array
(
[id] => 3657657
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[patent_title] => 'Semiconductor memory device and fabrication process'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/679319 | Semiconductor memory device and fabrication process | Jul 11, 1996 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/665532 | Polysilicon programming memory cell | Jun 17, 1996 | Issued |
Array
(
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[pdf_file] => patents/05/682/05682343.pdf
[firstpage_image] =>[orig_patent_app_number] => 664886
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/664886 | Hierarchical bit line arrangement in a semiconductor memory | Jun 16, 1996 | Issued |