Application number | Title of the application | Filing Date | Status |
---|
08/100202 | SEMICONDUCTOR MEMORY DEVICE HAVING A REDUNDANCY MEANS | Aug 1, 1993 | Pending |
08/099656 | MEMORY INTEGRATED CIRCUIT WITH PROTECTION AGAINST DISTURBANCES | Jul 29, 1993 | Pending |
Array
(
[id] => 3470763
[patent_doc_number] => 05392237
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-21
[patent_title] => 'Semiconductor memory device with EEPROM in trench with polysilicon/metal contacting to source and drain in virtual ground type array'
[patent_app_type] => 1
[patent_app_number] => 8/096995
[patent_app_country] => US
[patent_app_date] => 1993-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 23
[patent_no_of_words] => 3929
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/392/05392237.pdf
[firstpage_image] =>[orig_patent_app_number] => 096995
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/096995 | Semiconductor memory device with EEPROM in trench with polysilicon/metal contacting to source and drain in virtual ground type array | Jul 26, 1993 | Issued |
08/097805 | DISTRIBUTED SIGNAL DRIVERS IN ARRAYABLE DEVICES | Jul 25, 1993 | Pending |
Array
(
[id] => 3105406
[patent_doc_number] => 05293332
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Semiconductor memory device with switchable sense amps'
[patent_app_type] => 1
[patent_app_number] => 8/095195
[patent_app_country] => US
[patent_app_date] => 1993-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1664
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/293/05293332.pdf
[firstpage_image] =>[orig_patent_app_number] => 095195
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/095195 | Semiconductor memory device with switchable sense amps | Jul 22, 1993 | Issued |
08/089555 | FLASH EEPROM WITH ERASE VERIFICATION AND ADDRESS SCRAMBLING ARCHITECTURE | Jul 11, 1993 | Pending |
Array
(
[id] => 3024506
[patent_doc_number] => 05309392
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-03
[patent_title] => 'Semiconductor IC device using ferroelectric material in data storage cells with light assisted state transition'
[patent_app_type] => 1
[patent_app_number] => 8/086361
[patent_app_country] => US
[patent_app_date] => 1993-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 21
[patent_no_of_words] => 9664
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 239
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/309/05309392.pdf
[firstpage_image] =>[orig_patent_app_number] => 086361
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/086361 | Semiconductor IC device using ferroelectric material in data storage cells with light assisted state transition | Jul 5, 1993 | Issued |
Array
(
[id] => 3107369
[patent_doc_number] => 05299155
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-29
[patent_title] => 'Dynamic random access memory device with capacitor between vertically aligned FETs'
[patent_app_type] => 1
[patent_app_number] => 8/084442
[patent_app_country] => US
[patent_app_date] => 1993-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 36
[patent_no_of_words] => 2352
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/299/05299155.pdf
[firstpage_image] =>[orig_patent_app_number] => 084442
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/084442 | Dynamic random access memory device with capacitor between vertically aligned FETs | Jun 30, 1993 | Issued |
Array
(
[id] => 3067779
[patent_doc_number] => 05339270
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-16
[patent_title] => 'AC drain voltage charging source for PROM devices'
[patent_app_type] => 1
[patent_app_number] => 8/082124
[patent_app_country] => US
[patent_app_date] => 1993-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1237
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/339/05339270.pdf
[firstpage_image] =>[orig_patent_app_number] => 082124
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/082124 | AC drain voltage charging source for PROM devices | Jun 22, 1993 | Issued |
Array
(
[id] => 3541160
[patent_doc_number] => 05583810
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Method for programming a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/080225
[patent_app_country] => US
[patent_app_date] => 1993-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 5363
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583810.pdf
[firstpage_image] =>[orig_patent_app_number] => 080225
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/080225 | Method for programming a semiconductor memory device | Jun 20, 1993 | Issued |
Array
(
[id] => 3085932
[patent_doc_number] => 05323343
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-21
[patent_title] => 'DRAM device comprising a stacked type capacitor and a method of manufacturing thereof'
[patent_app_type] => 1
[patent_app_number] => 8/077971
[patent_app_country] => US
[patent_app_date] => 1993-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 47
[patent_no_of_words] => 9293
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/323/05323343.pdf
[firstpage_image] =>[orig_patent_app_number] => 077971
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/077971 | DRAM device comprising a stacked type capacitor and a method of manufacturing thereof | Jun 17, 1993 | Issued |
Array
(
[id] => 3006462
[patent_doc_number] => 05363324
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-08
[patent_title] => 'Full CMOS type SRAM and method of manufacturing same'
[patent_app_type] => 1
[patent_app_number] => 8/078150
[patent_app_country] => US
[patent_app_date] => 1993-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4768
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/363/05363324.pdf
[firstpage_image] =>[orig_patent_app_number] => 078150
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/078150 | Full CMOS type SRAM and method of manufacturing same | Jun 16, 1993 | Issued |
08/075306 | EEPROM ERASING AND PROGRAMMING METHOD | Jun 10, 1993 | Pending |
Array
(
[id] => 3032118
[patent_doc_number] => 05289404
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-22
[patent_title] => 'Semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/074706
[patent_app_country] => US
[patent_app_date] => 1993-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1873
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/289/05289404.pdf
[firstpage_image] =>[orig_patent_app_number] => 074706
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/074706 | Semiconductor memory device | Jun 8, 1993 | Issued |
08/067736 | SEMICONDUCTOR MEMORY OPERATING WITH LOW SUPPLY VOLTAGE | May 25, 1993 | Pending |
08/066884 | NON-VOLATILE MEMORY CELL AND ARRAY ARCHITECTURE | May 24, 1993 | Pending |
Array
(
[id] => 3019215
[patent_doc_number] => 05331592
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-19
[patent_title] => 'Non-volatile semiconductor memory device with erasure control circuit'
[patent_app_type] => 1
[patent_app_number] => 8/062396
[patent_app_country] => US
[patent_app_date] => 1993-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 3220
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/331/05331592.pdf
[firstpage_image] =>[orig_patent_app_number] => 062396
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/062396 | Non-volatile semiconductor memory device with erasure control circuit | May 16, 1993 | Issued |
Array
(
[id] => 3055506
[patent_doc_number] => 05287310
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Memory with I/O mappable redundant columns'
[patent_app_type] => 1
[patent_app_number] => 8/057405
[patent_app_country] => US
[patent_app_date] => 1993-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 10183
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/287/05287310.pdf
[firstpage_image] =>[orig_patent_app_number] => 057405
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/057405 | Memory with I/O mappable redundant columns | May 5, 1993 | Issued |
Array
(
[id] => 3064407
[patent_doc_number] => 05345422
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-06
[patent_title] => 'Power up detection circuit'
[patent_app_type] => 1
[patent_app_number] => 8/057589
[patent_app_country] => US
[patent_app_date] => 1993-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 191
[patent_figures_cnt] => 236
[patent_no_of_words] => 112590
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/345/05345422.pdf
[firstpage_image] =>[orig_patent_app_number] => 057589
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/057589 | Power up detection circuit | May 5, 1993 | Issued |
Array
(
[id] => 3114068
[patent_doc_number] => 05448512
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-05
[patent_title] => 'Semiconductor memory device with contact region intermediate memory cell and peripheral circuit'
[patent_app_type] => 1
[patent_app_number] => 8/044676
[patent_app_country] => US
[patent_app_date] => 1993-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 48
[patent_figures_cnt] => 57
[patent_no_of_words] => 5863
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/448/05448512.pdf
[firstpage_image] =>[orig_patent_app_number] => 044676
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/044676 | Semiconductor memory device with contact region intermediate memory cell and peripheral circuit | Apr 8, 1993 | Issued |