Search

Nora Maureen Rooney

Examiner (ID: 173, Phone: (571)272-9937 , Office: P/1644 )

Most Active Art Unit
1644
Art Unit(s)
1641, 1644
Total Applications
861
Issued Applications
413
Pending Applications
100
Abandoned Applications
348

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2830507 [patent_doc_number] => 05168468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-01 [patent_title] => 'Semiconductor memory device with column redundancy' [patent_app_type] => 1 [patent_app_number] => 7/789036 [patent_app_country] => US [patent_app_date] => 1991-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12253 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/168/05168468.pdf [firstpage_image] =>[orig_patent_app_number] => 789036 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/789036
Semiconductor memory device with column redundancy Nov 6, 1991 Issued
Array ( [id] => 2854027 [patent_doc_number] => 05138576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-11 [patent_title] => 'Method and apparatus for erasing an array of electrically erasable EPROM cells' [patent_app_type] => 1 [patent_app_number] => 7/788606 [patent_app_country] => US [patent_app_date] => 1991-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2512 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 404 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/138/05138576.pdf [firstpage_image] =>[orig_patent_app_number] => 788606 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/788606
Method and apparatus for erasing an array of electrically erasable EPROM cells Nov 5, 1991 Issued
Array ( [id] => 3598550 [patent_doc_number] => 05517445 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-14 [patent_title] => 'Non-volatile semiconductor memory device capable of electrically performing read and write operation and method of reading information from the same' [patent_app_type] => 1 [patent_app_number] => 7/784073 [patent_app_country] => US [patent_app_date] => 1991-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6083 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/517/05517445.pdf [firstpage_image] =>[orig_patent_app_number] => 784073 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/784073
Non-volatile semiconductor memory device capable of electrically performing read and write operation and method of reading information from the same Oct 29, 1991 Issued
Array ( [id] => 2824159 [patent_doc_number] => 05122986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Two transistor dram cell' [patent_app_type] => 1 [patent_app_number] => 7/785883 [patent_app_country] => US [patent_app_date] => 1991-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2425 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122986.pdf [firstpage_image] =>[orig_patent_app_number] => 785883 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/785883
Two transistor dram cell Oct 29, 1991 Issued
07/784971 MOS INTEGRATED CIRCUIT WITH ADJUSTABLE THRESHOLD VOLTAGE Oct 29, 1991 Abandoned
07/780389 DYNAMIC RANDOM ACCESS MEMORY DEVICE Oct 22, 1991 Abandoned
Array ( [id] => 2996454 [patent_doc_number] => 05212664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-18 [patent_title] => 'Information card with dual power detection signals to memory decoder' [patent_app_type] => 1 [patent_app_number] => 7/777445 [patent_app_country] => US [patent_app_date] => 1991-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3575 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/212/05212664.pdf [firstpage_image] =>[orig_patent_app_number] => 777445 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/777445
Information card with dual power detection signals to memory decoder Oct 15, 1991 Issued
Array ( [id] => 2847488 [patent_doc_number] => 05121360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Video random access memory serial port access' [patent_app_type] => 1 [patent_app_number] => 7/773736 [patent_app_country] => US [patent_app_date] => 1991-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4904 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121360.pdf [firstpage_image] =>[orig_patent_app_number] => 773736 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/773736
Video random access memory serial port access Oct 8, 1991 Issued
Array ( [id] => 3049645 [patent_doc_number] => 05377151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Semiconductor memory device having low-noise sense structure' [patent_app_type] => 1 [patent_app_number] => 7/767774 [patent_app_country] => US [patent_app_date] => 1991-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5572 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/377/05377151.pdf [firstpage_image] =>[orig_patent_app_number] => 767774 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/767774
Semiconductor memory device having low-noise sense structure Sep 29, 1991 Issued
Array ( [id] => 3044905 [patent_doc_number] => 05329513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Angular relationship detection device and method' [patent_app_type] => 1 [patent_app_number] => 7/766094 [patent_app_country] => US [patent_app_date] => 1991-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3793 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329513.pdf [firstpage_image] =>[orig_patent_app_number] => 766094 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/766094
Angular relationship detection device and method Sep 26, 1991 Issued
07/765505 SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF PREVENTING OCCURRENCE OF ERRONEOUS OPERATION DUE TO NOISE Sep 25, 1991 Abandoned
07/764688 DRAM DEVICE COMPRISING A STACKED TYPE CAPACITOR AND A METHOD OF MANUFACTURING THEREOF Sep 23, 1991 Abandoned
07/762116 SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING P-CHANNEL MOS TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES Sep 18, 1991 Abandoned
Array ( [id] => 3061289 [patent_doc_number] => 05325323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Erasable and programmable ROM with an identification code' [patent_app_type] => 1 [patent_app_number] => 7/762385 [patent_app_country] => US [patent_app_date] => 1991-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2434 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/325/05325323.pdf [firstpage_image] =>[orig_patent_app_number] => 762385 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/762385
Erasable and programmable ROM with an identification code Sep 18, 1991 Issued
Array ( [id] => 2908782 [patent_doc_number] => 05245582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Memory card circuit with power-down control of access buffer' [patent_app_type] => 1 [patent_app_number] => 7/760845 [patent_app_country] => US [patent_app_date] => 1991-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6042 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/245/05245582.pdf [firstpage_image] =>[orig_patent_app_number] => 760845 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/760845
Memory card circuit with power-down control of access buffer Sep 16, 1991 Issued
Array ( [id] => 3096299 [patent_doc_number] => 05285412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-08 [patent_title] => 'Semiconductor memory device with step-down transistor for external signal' [patent_app_type] => 1 [patent_app_number] => 7/759294 [patent_app_country] => US [patent_app_date] => 1991-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2690 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/285/05285412.pdf [firstpage_image] =>[orig_patent_app_number] => 759294 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/759294
Semiconductor memory device with step-down transistor for external signal Sep 12, 1991 Issued
Array ( [id] => 2896523 [patent_doc_number] => 05214610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-25 [patent_title] => 'Memory with selective address transition detection for cache operation' [patent_app_type] => 1 [patent_app_number] => 7/754281 [patent_app_country] => US [patent_app_date] => 1991-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 12233 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/214/05214610.pdf [firstpage_image] =>[orig_patent_app_number] => 754281 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/754281
Memory with selective address transition detection for cache operation Aug 29, 1991 Issued
Array ( [id] => 3075110 [patent_doc_number] => 05295095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-15 [patent_title] => 'Method of programming electrically erasable programmable read-only memory using particular substrate bias' [patent_app_type] => 1 [patent_app_number] => 7/748374 [patent_app_country] => US [patent_app_date] => 1991-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1612 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/295/05295095.pdf [firstpage_image] =>[orig_patent_app_number] => 748374 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/748374
Method of programming electrically erasable programmable read-only memory using particular substrate bias Aug 21, 1991 Issued
Array ( [id] => 2960512 [patent_doc_number] => 05262986 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Semiconductor memory device with volatile memory and non-volatile memory in latched arrangement' [patent_app_type] => 1 [patent_app_number] => 7/743893 [patent_app_country] => US [patent_app_date] => 1991-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2005 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/262/05262986.pdf [firstpage_image] =>[orig_patent_app_number] => 743893 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/743893
Semiconductor memory device with volatile memory and non-volatile memory in latched arrangement Aug 11, 1991 Issued
Array ( [id] => 2945056 [patent_doc_number] => 05229963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'Semiconductor nonvolatile memory device for controlling the potentials on bit lines' [patent_app_type] => 1 [patent_app_number] => 7/740665 [patent_app_country] => US [patent_app_date] => 1991-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 5032 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229963.pdf [firstpage_image] =>[orig_patent_app_number] => 740665 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/740665
Semiconductor nonvolatile memory device for controlling the potentials on bit lines Aug 1, 1991 Issued
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