Search

Nora Maureen Rooney

Examiner (ID: 173, Phone: (571)272-9937 , Office: P/1644 )

Most Active Art Unit
1644
Art Unit(s)
1641, 1644
Total Applications
861
Issued Applications
413
Pending Applications
100
Abandoned Applications
348

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3715767 [patent_doc_number] => 05654915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => '6-bulk transistor static memory cell using split wordline architecture' [patent_app_type] => 1 [patent_app_number] => 8/663603 [patent_app_country] => US [patent_app_date] => 1996-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4051 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654915.pdf [firstpage_image] =>[orig_patent_app_number] => 663603 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/663603
6-bulk transistor static memory cell using split wordline architecture Jun 13, 1996 Issued
Array ( [id] => 3741182 [patent_doc_number] => 05636162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Erase procedure' [patent_app_type] => 1 [patent_app_number] => 8/664013 [patent_app_country] => US [patent_app_date] => 1996-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4361 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636162.pdf [firstpage_image] =>[orig_patent_app_number] => 664013 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664013
Erase procedure Jun 11, 1996 Issued
Array ( [id] => 3644688 [patent_doc_number] => 05610863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Memory device having a booster circuit and a booster circuit control method' [patent_app_type] => 1 [patent_app_number] => 8/655915 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3551 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610863.pdf [firstpage_image] =>[orig_patent_app_number] => 655915 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655915
Memory device having a booster circuit and a booster circuit control method May 30, 1996 Issued
Array ( [id] => 3867554 [patent_doc_number] => 05706225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Memory apparatus with dynamic memory cells having different capacitor values' [patent_app_type] => 1 [patent_app_number] => 8/652915 [patent_app_country] => US [patent_app_date] => 1996-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1468 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706225.pdf [firstpage_image] =>[orig_patent_app_number] => 652915 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/652915
Memory apparatus with dynamic memory cells having different capacitor values May 19, 1996 Issued
Array ( [id] => 3630474 [patent_doc_number] => 05615152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Method of erasing a high density contactless flash EPROM array' [patent_app_type] => 1 [patent_app_number] => 8/648423 [patent_app_country] => US [patent_app_date] => 1996-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 3421 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615152.pdf [firstpage_image] =>[orig_patent_app_number] => 648423 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/648423
Method of erasing a high density contactless flash EPROM array May 14, 1996 Issued
Array ( [id] => 3892244 [patent_doc_number] => 05748525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Array cell circuit with split read/write line' [patent_app_type] => 1 [patent_app_number] => 8/643807 [patent_app_country] => US [patent_app_date] => 1996-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2889 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/748/05748525.pdf [firstpage_image] =>[orig_patent_app_number] => 643807 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/643807
Array cell circuit with split read/write line May 5, 1996 Issued
Array ( [id] => 3736592 [patent_doc_number] => 05652733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Command encoded delayed clock generator' [patent_app_type] => 1 [patent_app_number] => 8/638812 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3061 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652733.pdf [firstpage_image] =>[orig_patent_app_number] => 638812 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638812
Command encoded delayed clock generator Apr 28, 1996 Issued
Array ( [id] => 3764918 [patent_doc_number] => 05721703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Reprogrammable option select circuit' [patent_app_type] => 1 [patent_app_number] => 8/641114 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 4200 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721703.pdf [firstpage_image] =>[orig_patent_app_number] => 641114 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641114
Reprogrammable option select circuit Apr 28, 1996 Issued
Array ( [id] => 3699064 [patent_doc_number] => 05604698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Virtual-ground flash EPROM array with reduced cell pitch in the X direction' [patent_app_type] => 1 [patent_app_number] => 8/631824 [patent_app_country] => US [patent_app_date] => 1996-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 4631 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604698.pdf [firstpage_image] =>[orig_patent_app_number] => 631824 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/631824
Virtual-ground flash EPROM array with reduced cell pitch in the X direction Apr 9, 1996 Issued
08/626408 SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY CIRCUIT Apr 1, 1996 Abandoned
08/623731 DOUBLE POLYSILICON EEPROM CELL AND CORRESPONDING MANUFACTURING PROCESS AND PROGRAMMING METHOD Mar 28, 1996 Abandoned
Array ( [id] => 3798433 [patent_doc_number] => 05737260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Dual mode ferroelectric memory reference scheme' [patent_app_type] => 1 [patent_app_number] => 8/626614 [patent_app_country] => US [patent_app_date] => 1996-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6628 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737260.pdf [firstpage_image] =>[orig_patent_app_number] => 626614 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626614
Dual mode ferroelectric memory reference scheme Mar 26, 1996 Issued
Array ( [id] => 3657069 [patent_doc_number] => 05629891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Writable analog reference voltage storage device' [patent_app_type] => 1 [patent_app_number] => 8/622763 [patent_app_country] => US [patent_app_date] => 1996-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8463 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629891.pdf [firstpage_image] =>[orig_patent_app_number] => 622763 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/622763
Writable analog reference voltage storage device Mar 24, 1996 Issued
Array ( [id] => 3897581 [patent_doc_number] => 05715189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Semiconductor memory device having hierarchical bit line arrangement' [patent_app_type] => 1 [patent_app_number] => 8/614567 [patent_app_country] => US [patent_app_date] => 1996-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 10120 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/715/05715189.pdf [firstpage_image] =>[orig_patent_app_number] => 614567 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/614567
Semiconductor memory device having hierarchical bit line arrangement Mar 12, 1996 Issued
Array ( [id] => 3703185 [patent_doc_number] => 05650960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-22 [patent_title] => 'Polysilicon programming memory cell' [patent_app_type] => 1 [patent_app_number] => 8/615702 [patent_app_country] => US [patent_app_date] => 1996-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 20 [patent_no_of_words] => 3158 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/650/05650960.pdf [firstpage_image] =>[orig_patent_app_number] => 615702 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/615702
Polysilicon programming memory cell Mar 12, 1996 Issued
08/603381 FLASH EEPROM WITH ERASE VERIFICATION AND ADDRESS SCRAMBLING ARCHITECTURE Feb 19, 1996 Abandoned
Array ( [id] => 3636641 [patent_doc_number] => 05621696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Virtual multiple-read port memory array' [patent_app_type] => 1 [patent_app_number] => 8/626613 [patent_app_country] => US [patent_app_date] => 1996-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 924 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/621/05621696.pdf [firstpage_image] =>[orig_patent_app_number] => 626613 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626613
Virtual multiple-read port memory array Jan 25, 1996 Issued
Array ( [id] => 3657868 [patent_doc_number] => 05640360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Address buffer of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/591118 [patent_app_country] => US [patent_app_date] => 1996-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6119 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640360.pdf [firstpage_image] =>[orig_patent_app_number] => 591118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/591118
Address buffer of semiconductor memory device Jan 24, 1996 Issued
Array ( [id] => 3657826 [patent_doc_number] => 05638320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'High resolution analog storage EPROM and flash EPROM' [patent_app_type] => 1 [patent_app_number] => 8/585138 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 63 [patent_no_of_words] => 16449 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638320.pdf [firstpage_image] =>[orig_patent_app_number] => 585138 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/585138
High resolution analog storage EPROM and flash EPROM Jan 10, 1996 Issued
Array ( [id] => 3632844 [patent_doc_number] => 05612912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Method of multilevel DRAM sense and restore' [patent_app_type] => 1 [patent_app_number] => 8/584887 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5749 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612912.pdf [firstpage_image] =>[orig_patent_app_number] => 584887 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/584887
Method of multilevel DRAM sense and restore Jan 10, 1996 Issued
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