Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3563257
[patent_doc_number] => 05574696
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Dynamic ram device having high read operation speed'
[patent_app_type] => 1
[patent_app_number] => 8/333984
[patent_app_country] => US
[patent_app_date] => 1994-11-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/574/05574696.pdf
[firstpage_image] =>[orig_patent_app_number] => 333984
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/333984 | Dynamic ram device having high read operation speed | Nov 1, 1994 | Issued |
08/323604 | SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE CONTACT AREAS AND STORAGE CAPACITOR CONTACT AREAS | Oct 16, 1994 | Abandoned |
Array
(
[id] => 3612926
[patent_doc_number] => 05579264
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Distributed signal drivers in arrayable devices'
[patent_app_type] => 1
[patent_app_number] => 8/323428
[patent_app_country] => US
[patent_app_date] => 1994-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/579/05579264.pdf
[firstpage_image] =>[orig_patent_app_number] => 323428
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/323428 | Distributed signal drivers in arrayable devices | Oct 13, 1994 | Issued |
08/313605 | SEMICONDUCTOR MEMORY DEVICE AND FABRICATION PROCESS | Sep 28, 1994 | Abandoned |
08/311366 | 6-BULK TRANSISTOR STATIC MEMORY CELL USING SPLIT WORDLINE ARCHITECTURE | Sep 22, 1994 | Abandoned |
Array
(
[id] => 3437085
[patent_doc_number] => 05455792
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-03
[patent_title] => 'Flash EEPROM devices employing mid channel injection'
[patent_app_type] => 1
[patent_app_number] => 8/303361
[patent_app_country] => US
[patent_app_date] => 1994-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 19
[patent_no_of_words] => 10363
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[pdf_file] => patents/05/455/05455792.pdf
[firstpage_image] =>[orig_patent_app_number] => 303361
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/303361 | Flash EEPROM devices employing mid channel injection | Sep 8, 1994 | Issued |
Array
(
[id] => 3563109
[patent_doc_number] => 05574685
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Self-aligned buried channel/junction stacked gate flash memory cell'
[patent_app_type] => 1
[patent_app_number] => 8/299876
[patent_app_country] => US
[patent_app_date] => 1994-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 2639
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[pdf_file] => patents/05/574/05574685.pdf
[firstpage_image] =>[orig_patent_app_number] => 299876
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/299876 | Self-aligned buried channel/junction stacked gate flash memory cell | Aug 31, 1994 | Issued |
Array
(
[id] => 3455538
[patent_doc_number] => 05420816
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-30
[patent_title] => 'Semiconductor memory apparatus with configured word lines to reduce noise'
[patent_app_type] => 1
[patent_app_number] => 8/299086
[patent_app_country] => US
[patent_app_date] => 1994-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 4321
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/420/05420816.pdf
[firstpage_image] =>[orig_patent_app_number] => 299086
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/299086 | Semiconductor memory apparatus with configured word lines to reduce noise | Aug 30, 1994 | Issued |
Array
(
[id] => 3468432
[patent_doc_number] => 05383149
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-17
[patent_title] => 'Ulsi mask ROM structure and method of manufacture'
[patent_app_type] => 1
[patent_app_number] => 8/294855
[patent_app_country] => US
[patent_app_date] => 1994-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 3514
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/383/05383149.pdf
[firstpage_image] =>[orig_patent_app_number] => 294855
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/294855 | Ulsi mask ROM structure and method of manufacture | Aug 28, 1994 | Issued |
08/291615 | MULTIPLE PAGE MEMORY | Aug 16, 1994 | Abandoned |
08/291692 | VOLTAGE MULTIPLIER CIRCUIT AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING VOLTAGE MULTIPLIER CIRCUIT | Aug 15, 1994 | Abandoned |
08/288776 | HIERARCHICAL BIT LINE ARRANGEMENT IN A SEMICONDUCTOR MEMORY DEVICE | Aug 10, 1994 | Abandoned |
Array
(
[id] => 3563638
[patent_doc_number] => 05519661
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-21
[patent_title] => 'Semiconductor memory circuit with bit line detector controlling access to data bus lines'
[patent_app_type] => 1
[patent_app_number] => 8/281835
[patent_app_country] => US
[patent_app_date] => 1994-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2098
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/519/05519661.pdf
[firstpage_image] =>[orig_patent_app_number] => 281835
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/281835 | Semiconductor memory circuit with bit line detector controlling access to data bus lines | Jul 27, 1994 | Issued |
Array
(
[id] => 3125634
[patent_doc_number] => 05410506
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-25
[patent_title] => 'Memory integrated circuit with protection against disturbances'
[patent_app_type] => 1
[patent_app_number] => 8/274142
[patent_app_country] => US
[patent_app_date] => 1994-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2380
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/410/05410506.pdf
[firstpage_image] =>[orig_patent_app_number] => 274142
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/274142 | Memory integrated circuit with protection against disturbances | Jul 13, 1994 | Issued |
Array
(
[id] => 3541174
[patent_doc_number] => 05583811
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Transistor structure for erasable and programmable semiconductor memory devices'
[patent_app_type] => 1
[patent_app_number] => 8/275016
[patent_app_country] => US
[patent_app_date] => 1994-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 5700
[patent_no_of_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583811.pdf
[firstpage_image] =>[orig_patent_app_number] => 275016
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/275016 | Transistor structure for erasable and programmable semiconductor memory devices | Jul 12, 1994 | Issued |
Array
(
[id] => 3844439
[patent_doc_number] => 05761119
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Nonvolatile semiconductor memory with a plurality of erase decoders connected to erase gates'
[patent_app_type] => 1
[patent_app_number] => 8/273922
[patent_app_country] => US
[patent_app_date] => 1994-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 21
[patent_no_of_words] => 6393
[patent_no_of_claims] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/761/05761119.pdf
[firstpage_image] =>[orig_patent_app_number] => 273922
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/273922 | Nonvolatile semiconductor memory with a plurality of erase decoders connected to erase gates | Jul 11, 1994 | Issued |
Array
(
[id] => 3565973
[patent_doc_number] => 05544103
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Compact page-erasable eeprom non-volatile memory'
[patent_app_type] => 1
[patent_app_number] => 8/273612
[patent_app_country] => US
[patent_app_date] => 1994-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 27143
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/544/05544103.pdf
[firstpage_image] =>[orig_patent_app_number] => 273612
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/273612 | Compact page-erasable eeprom non-volatile memory | Jul 11, 1994 | Issued |
Array
(
[id] => 3537272
[patent_doc_number] => 05541878
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Writable analog reference voltage storage device'
[patent_app_type] => 1
[patent_app_number] => 8/267595
[patent_app_country] => US
[patent_app_date] => 1994-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/541/05541878.pdf
[firstpage_image] =>[orig_patent_app_number] => 267595
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/267595 | Writable analog reference voltage storage device | Jun 26, 1994 | Issued |
Array
(
[id] => 3464090
[patent_doc_number] => 05452250
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-19
[patent_title] => 'Non-volatile register system utilizing thin-film floating-gate amorphous transistors'
[patent_app_type] => 1
[patent_app_number] => 8/261356
[patent_app_country] => US
[patent_app_date] => 1994-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4435
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/452/05452250.pdf
[firstpage_image] =>[orig_patent_app_number] => 261356
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/261356 | Non-volatile register system utilizing thin-film floating-gate amorphous transistors | Jun 13, 1994 | Issued |
08/253435 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME | Jun 5, 1994 | Abandoned |