Search

Norca Liz Torres Velazquez

Examiner (ID: 4407, Phone: (571)272-1484 , Office: P/3991 )

Most Active Art Unit
1771
Art Unit(s)
1786, 1771, OPLA, 3991, 1763, 1794
Total Applications
823
Issued Applications
509
Pending Applications
40
Abandoned Applications
273

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18774284 [patent_doc_number] => 20230369115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => PACKAGE STRUCTURE WITH FAN-OUT FEATURE [patent_app_type] => utility [patent_app_number] => 18/360581 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360581 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360581
Package structure with fan-out feature Jul 26, 2023 Issued
Array ( [id] => 18774393 [patent_doc_number] => 20230369224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => VIA FOR SEMICONDUCTOR DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/358803 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358803 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358803
Via for semiconductor device and method Jul 24, 2023 Issued
Array ( [id] => 18821348 [patent_doc_number] => 20230395689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => Method for Fabricating Metal Gate Devices and Resulting Structures [patent_app_type] => utility [patent_app_number] => 18/358742 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358742 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358742
Method for fabricating metal gate devices and resulting structures Jul 24, 2023 Issued
Array ( [id] => 18714785 [patent_doc_number] => 20230337429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => Memory Arrays and Methods Used in Forming a Memory Array Comprising Strings of Memory Cells [patent_app_type] => utility [patent_app_number] => 18/212899 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212899 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212899
Memory arrays and methods used in forming a memory array comprising strings of memory cells Jun 21, 2023 Issued
Array ( [id] => 18865956 [patent_doc_number] => 20230420393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/327390 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327390 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327390
SEMICONDUCTOR PACKAGE May 31, 2023 Pending
Array ( [id] => 19604730 [patent_doc_number] => 20240395610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => STRUCTURES FOR REDUCING GAP FILL DEFECTS IN A VERTICALLY STACKED SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/323455 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323455 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323455
STRUCTURES FOR REDUCING GAP FILL DEFECTS IN A VERTICALLY STACKED SEMICONDUCTOR DEVICE AND METHODS FOR FORMING THE SAME May 24, 2023 Pending
Array ( [id] => 19116391 [patent_doc_number] => 20240128141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => MULTI-CHIP PACKAGING METHOD AND MULTI-CHIP PACKAGING STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/196530 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18196530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/196530
MULTI-CHIP PACKAGING METHOD AND MULTI-CHIP PACKAGING STRUCTURE May 11, 2023 Pending
Array ( [id] => 18975293 [patent_doc_number] => 20240055385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/315537 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315537
PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME May 10, 2023 Pending
Array ( [id] => 19261085 [patent_doc_number] => 12021152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Process to reduce plasma induced damage [patent_app_type] => utility [patent_app_number] => 18/307846 [patent_app_country] => US [patent_app_date] => 2023-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/307846
Process to reduce plasma induced damage Apr 26, 2023 Issued
Array ( [id] => 18586206 [patent_doc_number] => 20230268471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 18/307015 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307015 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/307015
Light emitting device Apr 25, 2023 Issued
Array ( [id] => 18514656 [patent_doc_number] => 20230230917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/125529 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18125529 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/125529
Semiconductor package Mar 22, 2023 Issued
Array ( [id] => 18488491 [patent_doc_number] => 20230215839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => LOGIC DRIVE BASED ON CHIP SCALE PACKAGE COMPRISING STANDARDIZED COMMODITY PROGRAMMABLE LOGIC IC CHIP AND MEMORY IC CHIP [patent_app_type] => utility [patent_app_number] => 18/121873 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 97484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 488 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18121873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/121873
Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip Mar 14, 2023 Issued
Array ( [id] => 18555231 [patent_doc_number] => 20230253248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => METHODS OF FORMING METAL LINER FOR INTERCONNECT STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/119080 [patent_app_country] => US [patent_app_date] => 2023-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9485 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119080
METHODS OF FORMING METAL LINER FOR INTERCONNECT STRUCTURES Mar 7, 2023 Pending
Array ( [id] => 19349294 [patent_doc_number] => 20240258258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING BALL GRID ARRAY CONNECTIONS WITH IMPROVED RELIABILITY [patent_app_type] => utility [patent_app_number] => 18/103698 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103698 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103698
SEMICONDUCTOR PACKAGE INCLUDING BALL GRID ARRAY CONNECTIONS WITH IMPROVED RELIABILITY Jan 30, 2023 Pending
Array ( [id] => 18814956 [patent_doc_number] => 20230389294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => TRANSISTOR, MANUFACTURING METHOD THEREOF, AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/151434 [patent_app_country] => US [patent_app_date] => 2023-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8875 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151434 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151434
TRANSISTOR, MANUFACTURING METHOD THEREOF, AND MEMORY Jan 6, 2023 Pending
Array ( [id] => 20334467 [patent_doc_number] => 12464763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Hybrid nanostructure and fin structure device [patent_app_type] => utility [patent_app_number] => 18/149242 [patent_app_country] => US [patent_app_date] => 2023-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/149242
Hybrid nanostructure and fin structure device Jan 2, 2023 Issued
Array ( [id] => 18339808 [patent_doc_number] => 20230131757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => GATE LINE PLUG STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION [patent_app_type] => utility [patent_app_number] => 18/088461 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 73931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088461 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088461
GATE LINE PLUG STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION Dec 22, 2022 Pending
Array ( [id] => 18268553 [patent_doc_number] => 20230089795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/994004 [patent_app_country] => US [patent_app_date] => 2022-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8638 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994004 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994004
Semiconductor package Nov 24, 2022 Issued
Array ( [id] => 18919199 [patent_doc_number] => 11881489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 17/991893 [patent_app_country] => US [patent_app_date] => 2022-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 117 [patent_no_of_words] => 33286 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 503 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17991893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/991893
Display device Nov 21, 2022 Issued
Array ( [id] => 19191504 [patent_doc_number] => 20240170417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => STIFFENER FOR A SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/056499 [patent_app_country] => US [patent_app_date] => 2022-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18056499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/056499
STIFFENER FOR A SEMICONDUCTOR PACKAGE Nov 16, 2022 Pending
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