Search

Norca Liz Torres Velazquez

Examiner (ID: 4407, Phone: (571)272-1484 , Office: P/3991 )

Most Active Art Unit
1771
Art Unit(s)
1786, 1771, OPLA, 3991, 1763, 1794
Total Applications
823
Issued Applications
509
Pending Applications
40
Abandoned Applications
273

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20334474 [patent_doc_number] => 12464770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Semiconductor devices having vertical channel transistor structures and methods of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/578893 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 4526 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578893 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/578893
Semiconductor devices having vertical channel transistor structures and methods of fabricating the same Jan 18, 2022 Issued
Array ( [id] => 17752905 [patent_doc_number] => 20220231110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/577920 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577920 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577920
DISPLAY DEVICE Jan 17, 2022 Pending
Array ( [id] => 17963843 [patent_doc_number] => 20220344424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/568242 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18333 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568242
Display device and method of manufacturing display device Jan 3, 2022 Issued
Array ( [id] => 18179302 [patent_doc_number] => 20230040031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => METHOD OF FORMING METAL GRID, BACKSIDE-ILLUMINATED IMAGE SENSOR AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/566386 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566386
Method of forming metal grid, backside-illuminated image sensor and method of forming the same Dec 29, 2021 Issued
Array ( [id] => 19900240 [patent_doc_number] => 12278177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Semiconductor device manufacturing method [patent_app_type] => utility [patent_app_number] => 17/521959 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 1094 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/521959
Semiconductor device manufacturing method Nov 8, 2021 Issued
Array ( [id] => 17630679 [patent_doc_number] => 20220165694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/510348 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510348 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510348
SEMICONDUCTOR STRUCTURE Oct 24, 2021 Abandoned
Array ( [id] => 18271944 [patent_doc_number] => 20230093186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SEMICONDUCTOR DEVICE HAVING SOLDER-FREE DIE CONNECTION TO REDISTRIBUTION LAYER [patent_app_type] => utility [patent_app_number] => 17/479871 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479871 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479871
SEMICONDUCTOR DEVICE HAVING SOLDER-FREE DIE CONNECTION TO REDISTRIBUTION LAYER Sep 19, 2021 Pending
Array ( [id] => 20317447 [patent_doc_number] => 12455999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level [patent_app_type] => utility [patent_app_number] => 17/473039 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473039
Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level Sep 12, 2021 Issued
Array ( [id] => 18241512 [patent_doc_number] => 20230073823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => PACKAGE COMPRISING A SUBSTRATE WITH HIGH-DENSITY INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/471061 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471061 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471061
PACKAGE COMPRISING A SUBSTRATE WITH HIGH-DENSITY INTERCONNECTS Sep 8, 2021 Abandoned
Array ( [id] => 19733742 [patent_doc_number] => 12211743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Method of forming a metal liner for interconnect structures [patent_app_type] => utility [patent_app_number] => 17/466732 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9291 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/466732
Method of forming a metal liner for interconnect structures Sep 2, 2021 Issued
Array ( [id] => 17847923 [patent_doc_number] => 11437308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Packaging glass substrate for semiconductor, a packaging substrate for semiconductor, and a semiconductor apparatus [patent_app_type] => utility [patent_app_number] => 17/462254 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11741 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462254 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462254
Packaging glass substrate for semiconductor, a packaging substrate for semiconductor, and a semiconductor apparatus Aug 30, 2021 Issued
Array ( [id] => 19828763 [patent_doc_number] => 12249555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Semiconductor device package including a thermal conductive layer and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/380360 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380360 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380360
Semiconductor device package including a thermal conductive layer and methods of forming the same Jul 19, 2021 Issued
Array ( [id] => 17963790 [patent_doc_number] => 20220344371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => ARRAYED SWITCH CIRCUIT, SWITCHING ELEMENT AND SYSTEM CHIP PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/372132 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372132
Arrayed switch circuit, switching element and system chip package structure Jul 8, 2021 Issued
Array ( [id] => 18061774 [patent_doc_number] => 20220392861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => ELECTRONIC PACKAGE AND CARRIER THEREOF AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/369029 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369029 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369029
Electronic package and carrier thereof and method for manufacturing the same Jul 6, 2021 Issued
Array ( [id] => 17347124 [patent_doc_number] => 20220013455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/361460 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17361460 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/361460
WIRING SUBSTRATE AND METHOD FOR MANUFACTURING WIRING SUBSTRATE Jun 28, 2021 Pending
Array ( [id] => 18097535 [patent_doc_number] => 20220415876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => CONTROLLED ELECTROSTATIC DISCHARGING TO AVOID LOADING ON INPUT/OUTPUT PINS [patent_app_type] => utility [patent_app_number] => 17/360832 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360832
CONTROLLED ELECTROSTATIC DISCHARGING TO AVOID LOADING ON INPUT/OUTPUT PINS Jun 27, 2021 Abandoned
Array ( [id] => 18068176 [patent_doc_number] => 20220399264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUIT PACKAGE AND THE METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/343942 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343942
INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUIT PACKAGE AND THE METHOD THEREOF Jun 9, 2021 Abandoned
Array ( [id] => 17752773 [patent_doc_number] => 20220230978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => HYBRID MICRO-BUMP INTEGRATION WITH REDISTRIBUTION LAYER [patent_app_type] => utility [patent_app_number] => 17/326941 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326941
Hybrid micro-bump integration with redistribution layer May 20, 2021 Issued
Array ( [id] => 17070758 [patent_doc_number] => 20210272975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => REPLACEMENT CONTROL GATE METHODS AND APPARATUSES [patent_app_type] => utility [patent_app_number] => 17/322390 [patent_app_country] => US [patent_app_date] => 2021-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/322390
REPLACEMENT CONTROL GATE METHODS AND APPARATUSES May 16, 2021 Pending
Array ( [id] => 17318918 [patent_doc_number] => 20210407968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => DEVICE INCLUDING FIRST STRUCTURE HAVING PERIPHERAL CIRCUIT AND SECOND STRUCTURE HAVING GATE LAYERS [patent_app_type] => utility [patent_app_number] => 17/315716 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315716
Device including first structure having peripheral circuit and second structure having gate layers May 9, 2021 Issued
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