Search

Norca Liz Torres Velazquez

Examiner (ID: 4407, Phone: (571)272-1484 , Office: P/3991 )

Most Active Art Unit
1771
Art Unit(s)
1786, 1771, OPLA, 3991, 1763, 1794
Total Applications
823
Issued Applications
509
Pending Applications
40
Abandoned Applications
273

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16272487 [patent_doc_number] => 20200273975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => NITRIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 15/930070 [patent_app_country] => US [patent_app_date] => 2020-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15930070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/930070
Nitride semiconductor device and fabrication method therefor May 11, 2020 Issued
Array ( [id] => 17217822 [patent_doc_number] => 20210351160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => MITIGATING THERMAL IMPACTS ON ADJACENT STACKED SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/871490 [patent_app_country] => US [patent_app_date] => 2020-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4024 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871490 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/871490
Mitigating thermal impacts on adjacent stacked semiconductor devices May 10, 2020 Issued
Array ( [id] => 16528764 [patent_doc_number] => 20200402845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/863007 [patent_app_country] => US [patent_app_date] => 2020-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16863007 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/863007
SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF Apr 29, 2020 Abandoned
Array ( [id] => 16210691 [patent_doc_number] => 20200243681 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => REDUCTION OF TOP SOURCE/DRAIN EXTERNAL RESISTANCE AND PARASITIC CAPACITANCE IN VERTICAL TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/845350 [patent_app_country] => US [patent_app_date] => 2020-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/845350
Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors Apr 9, 2020 Issued
Array ( [id] => 17130353 [patent_doc_number] => 20210305122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-30 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/835322 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16835322 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/835322
Semiconductor package and manufacturing method thereof Mar 30, 2020 Issued
Array ( [id] => 19552852 [patent_doc_number] => 12136564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Superstrate and method of making it [patent_app_type] => utility [patent_app_number] => 16/834465 [patent_app_country] => US [patent_app_date] => 2020-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5278 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16834465 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/834465
Superstrate and method of making it Mar 29, 2020 Issued
Array ( [id] => 16180303 [patent_doc_number] => 20200227272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => Interconnect Structure with Porous Low K Film [patent_app_type] => utility [patent_app_number] => 16/831336 [patent_app_country] => US [patent_app_date] => 2020-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4110 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16831336 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/831336
Interconnect Structure with Porous Low K Film Mar 25, 2020 Abandoned
Array ( [id] => 17730837 [patent_doc_number] => 11387239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Semiconductor memory device structure [patent_app_type] => utility [patent_app_number] => 16/810572 [patent_app_country] => US [patent_app_date] => 2020-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5505 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810572 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/810572
Semiconductor memory device structure Mar 4, 2020 Issued
Array ( [id] => 19886919 [patent_doc_number] => 12272650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Microelectronic package with substrate cavity for bridge-attach [patent_app_type] => utility [patent_app_number] => 16/804835 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8705 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16804835 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/804835
Microelectronic package with substrate cavity for bridge-attach Feb 27, 2020 Issued
Array ( [id] => 16586103 [patent_doc_number] => 20210020505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/797990 [patent_app_country] => US [patent_app_date] => 2020-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16797990 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/797990
METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE Feb 20, 2020 Abandoned
Array ( [id] => 18120708 [patent_doc_number] => 11552107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Display device [patent_app_type] => utility [patent_app_number] => 16/793543 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 117 [patent_no_of_words] => 33280 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793543 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/793543
Display device Feb 17, 2020 Issued
Array ( [id] => 17551799 [patent_doc_number] => 20220123141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SILICON CARBIDE SEMICONDUCTOR CHIP AND SILICON CARBIDE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/429513 [patent_app_country] => US [patent_app_date] => 2020-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17429513 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/429513
SILICON CARBIDE SEMICONDUCTOR CHIP AND SILICON CARBIDE SEMICONDUCTOR DEVICE Jan 28, 2020 Abandoned
Array ( [id] => 15906533 [patent_doc_number] => 20200152787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => LATERAL INSULATED-GATE BIPOLAR TRANSISTOR AND METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/747264 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747264 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747264
Lateral insulated-gate bipolar transistor and method therefor Jan 19, 2020 Issued
Array ( [id] => 18766916 [patent_doc_number] => 11817325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Methods of manufacturing a semiconductor package [patent_app_type] => utility [patent_app_number] => 16/746192 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746192
Methods of manufacturing a semiconductor package Jan 16, 2020 Issued
Array ( [id] => 17224704 [patent_doc_number] => 11177214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Interconnects with hybrid metal conductors [patent_app_type] => utility [patent_app_number] => 16/743247 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 6018 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743247 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743247
Interconnects with hybrid metal conductors Jan 14, 2020 Issued
Array ( [id] => 17284126 [patent_doc_number] => 11201168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Semiconductor devices including flared source structures [patent_app_type] => utility [patent_app_number] => 16/735085 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 9762 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735085 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735085
Semiconductor devices including flared source structures Jan 5, 2020 Issued
Array ( [id] => 15807503 [patent_doc_number] => 20200126894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => INTEGRATED PASSIVE DEVICE AND FABRICATION METHOD USING A LAST THROUGH-SUBSTRATE VIA [patent_app_type] => utility [patent_app_number] => 16/722419 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16722419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/722419
Integrated passive device and fabrication method using a last through-substrate via Dec 19, 2019 Issued
Array ( [id] => 16684518 [patent_doc_number] => 10944010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/720151 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 13262 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720151
Semiconductor device Dec 18, 2019 Issued
Array ( [id] => 15807541 [patent_doc_number] => 20200126913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => Method of Preventing Pattern Collapse [patent_app_type] => utility [patent_app_number] => 16/719626 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719626 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719626
Method of preventing pattern collapse Dec 17, 2019 Issued
Array ( [id] => 16904949 [patent_doc_number] => 20210183865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR STRUCTURE FORMATION [patent_app_type] => utility [patent_app_number] => 16/711531 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16711531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/711531
Semiconductor structure formation at differential depths Dec 11, 2019 Issued
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