Search

Octavia L. Davis-hollington

Examiner (ID: 12421, Phone: (571)272-2176 , Office: P/2855 )

Most Active Art Unit
2855
Art Unit(s)
2856, 2855
Total Applications
1929
Issued Applications
1579
Pending Applications
125
Abandoned Applications
245

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16934660 [patent_doc_number] => 20210200549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => SYSTEMS, APPARATUSES, AND METHODS FOR 512-BIT OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/728785 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13065 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728785 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728785
SYSTEMS, APPARATUSES, AND METHODS FOR 512-BIT OPERATIONS Dec 26, 2019 Abandoned
Array ( [id] => 16385177 [patent_doc_number] => 10810012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Computer vision implementing calculations of window sums in overlapping windows [patent_app_type] => utility [patent_app_number] => 16/720808 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16720808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/720808
Computer vision implementing calculations of window sums in overlapping windows Dec 18, 2019 Issued
Array ( [id] => 16017701 [patent_doc_number] => 20200183694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => CALCULATION PROCESSING APPARATUS AND METHOD OF CONTROLLING CALCULATION PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/697244 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697244
Inhibiting load instruction execution based on reserving a resource of a load and store queue but failing to reserve a resource of a store data queue Nov 26, 2019 Issued
Array ( [id] => 16856856 [patent_doc_number] => 20210157601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => EXCEPTION INTERCEPTION [patent_app_type] => utility [patent_app_number] => 16/695745 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14220 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695745
Exception interception Nov 25, 2019 Issued
Array ( [id] => 16856853 [patent_doc_number] => 20210157598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => REGISTER WRITE SUPPRESSION [patent_app_type] => utility [patent_app_number] => 16/697147 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/697147
Suppressing allocation of registers for register renaming Nov 25, 2019 Issued
Array ( [id] => 16856852 [patent_doc_number] => 20210157597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => SPECULATIVE BUFFER [patent_app_type] => utility [patent_app_number] => 16/695735 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16889 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695735 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695735
Speculative buffer for speculative memory accesses with entries tagged with execution context identifiers Nov 25, 2019 Issued
Array ( [id] => 17454791 [patent_doc_number] => 11269650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Pipeline protection for CPUs with save and restore of intermediate results [patent_app_type] => utility [patent_app_number] => 16/685747 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9101 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685747 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/685747
Pipeline protection for CPUs with save and restore of intermediate results Nov 14, 2019 Issued
Array ( [id] => 16848931 [patent_doc_number] => 20210149676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => Branch Prediction Method, Branch Prediction Unit and Processor Core [patent_app_type] => utility [patent_app_number] => 16/683527 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683527
Branch Prediction Method, Branch Prediction Unit and Processor Core Nov 13, 2019 Abandoned
Array ( [id] => 16299882 [patent_doc_number] => 20200285605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SYSTOLIC ARRAY AND PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/684246 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684246 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684246
MxN systolic array and processing system that inputs weights to rows or columns based on mode to increase utilization of processing elements Nov 13, 2019 Issued
Array ( [id] => 16116337 [patent_doc_number] => 20200210191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => EXIT HISTORY BASED BRANCH PREDICTION [patent_app_type] => utility [patent_app_number] => 16/684410 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684410 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/684410
Exit history based branch prediction Nov 13, 2019 Issued
Array ( [id] => 16501640 [patent_doc_number] => 10867028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Program-instruction-controlled instruction flow supervision [patent_app_type] => utility [patent_app_number] => 16/678397 [patent_app_country] => US [patent_app_date] => 2019-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 13417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16678397 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/678397
Program-instruction-controlled instruction flow supervision Nov 7, 2019 Issued
Array ( [id] => 16810430 [patent_doc_number] => 20210132985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => SHADOW LATCHES IN A SHADOW-LATCH CONFIGURED REGISTER FILE FOR THREAD STORAGE [patent_app_type] => utility [patent_app_number] => 16/668469 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6015 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16668469 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/668469
SHADOW LATCHES IN A SHADOW-LATCH CONFIGURED REGISTER FILE FOR THREAD STORAGE Oct 29, 2019 Abandoned
Array ( [id] => 17009319 [patent_doc_number] => 20210240480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => A SYSTEM AND METHOD FOR HANDLING EXCEPTION CAUSING EVENTS [patent_app_type] => utility [patent_app_number] => 17/269938 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17269938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/269938
System and method for physically separating, across different processing units, software for handling exception causing events from executing program code Oct 15, 2019 Issued
Array ( [id] => 17744315 [patent_doc_number] => 11392382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Using a graph based micro-BTB and inverted basic block queue to efficiently identify program kernels that will fit in a micro-op cache [patent_app_type] => utility [patent_app_number] => 16/578257 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16578257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/578257
Using a graph based micro-BTB and inverted basic block queue to efficiently identify program kernels that will fit in a micro-op cache Sep 19, 2019 Issued
Array ( [id] => 16910340 [patent_doc_number] => 11042379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Apparatus and method for providing decoded instructions from a decoded instruction cache [patent_app_type] => utility [patent_app_number] => 16/575659 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9323 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575659 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/575659
Apparatus and method for providing decoded instructions from a decoded instruction cache Sep 18, 2019 Issued
Array ( [id] => 17252842 [patent_doc_number] => 11188331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Processor instruction specifying indexed storage region holding control data for swizzle operation [patent_app_type] => utility [patent_app_number] => 16/576505 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 10271 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576505 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/576505
Processor instruction specifying indexed storage region holding control data for swizzle operation Sep 18, 2019 Issued
Array ( [id] => 15215069 [patent_doc_number] => 20190370221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => CONDITIONAL OPERATION IN AN INTERNAL PROCESSOR OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/545907 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545907
Conditional operation in an internal processor of a memory device Aug 19, 2019 Issued
Array ( [id] => 16833919 [patent_doc_number] => 11010170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Arithmetic processing apparatus which replaces values for future branch prediction upon wrong branch prediction [patent_app_type] => utility [patent_app_number] => 16/536354 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 11149 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536354 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536354
Arithmetic processing apparatus which replaces values for future branch prediction upon wrong branch prediction Aug 8, 2019 Issued
Array ( [id] => 16833950 [patent_doc_number] => 11010202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Distributed physical processing of matrix sum operation [patent_app_type] => utility [patent_app_number] => 16/533588 [patent_app_country] => US [patent_app_date] => 2019-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533588 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/533588
Distributed physical processing of matrix sum operation Aug 5, 2019 Issued
Array ( [id] => 16623471 [patent_doc_number] => 20210042124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SHARING INSTRUCTION ENCODING SPACE [patent_app_type] => utility [patent_app_number] => 16/531295 [patent_app_country] => US [patent_app_date] => 2019-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531295 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/531295
Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry Aug 4, 2019 Issued
Menu