Search

Octavia L. Davis-hollington

Examiner (ID: 12421, Phone: (571)272-2176 , Office: P/2855 )

Most Active Art Unit
2855
Art Unit(s)
2856, 2855
Total Applications
1929
Issued Applications
1579
Pending Applications
125
Abandoned Applications
245

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20447099 [patent_doc_number] => 20260003821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => DISPATCH FOR A CONFIGURABLE DATA-FLOW COMPUTE ARRAY AND DATA-PARALLEL COMPUTE UNITS [patent_app_type] => utility [patent_app_number] => 18/754873 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754873
DISPATCH FOR A CONFIGURABLE DATA-FLOW COMPUTE ARRAY AND DATA-PARALLEL COMPUTE UNITS Jun 25, 2024 Pending
Array ( [id] => 20446902 [patent_doc_number] => 20260003624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => MULTI-INSTRUCTION FUSION [patent_app_type] => utility [patent_app_number] => 18/754278 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754278 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754278
MULTI-INSTRUCTION FUSION Jun 25, 2024 Pending
Array ( [id] => 20428219 [patent_doc_number] => 20250390309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => TECHNIQUE FOR GENERATING PREDICTIONS OF A TARGET ADDRESS OF BRANCH INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/753513 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10941 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753513 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753513
TECHNIQUE FOR GENERATING PREDICTIONS OF A TARGET ADDRESS OF BRANCH INSTRUCTIONS Jun 24, 2024 Pending
Array ( [id] => 20731816 [patent_doc_number] => 12639074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Prediction circuitry using a prediction table providing a skip-fetch-instruction entry [patent_app_type] => utility [patent_app_number] => 18/745756 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7098 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745756 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/745756
Prediction circuitry using a prediction table providing a skip-fetch-instruction entry Jun 16, 2024 Issued
Array ( [id] => 19481946 [patent_doc_number] => 20240329988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => Load Instruction Fusion [patent_app_type] => utility [patent_app_number] => 18/739070 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739070
Load instruction fusion Jun 9, 2024 Issued
Array ( [id] => 20395275 [patent_doc_number] => 20250370750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => UNALIGNED LOAD AND STORE IN A CORE [patent_app_type] => utility [patent_app_number] => 18/731006 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731006 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/731006
UNALIGNED LOAD AND STORE IN A CORE May 30, 2024 Pending
Array ( [id] => 20395280 [patent_doc_number] => 20250370755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => PHYSICAL REGISTER DEALLOCATION IN A PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/680032 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680032 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680032
PHYSICAL REGISTER DEALLOCATION IN A PROCESSING SYSTEM May 30, 2024 Pending
Array ( [id] => 19466338 [patent_doc_number] => 20240320008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => VARIABLE HISTORY LENGTH PERCEPTRON BRANCH PREDICTOR [patent_app_type] => utility [patent_app_number] => 18/680778 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680778
VARIABLE HISTORY LENGTH PERCEPTRON BRANCH PREDICTOR May 30, 2024 Pending
Array ( [id] => 20395241 [patent_doc_number] => 20250370716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => SELF-PROVISIONING AND FLEXIBLE HARDWARE ACCELERATOR ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/678861 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18678861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/678861
SELF-PROVISIONING AND FLEXIBLE HARDWARE ACCELERATOR ARCHITECTURE May 29, 2024 Pending
Array ( [id] => 19617367 [patent_doc_number] => 20240403047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => VECTOR COMPUTATION APPARATUS, PROCESSOR, SYSTEM ON CHIP AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/671202 [patent_app_country] => US [patent_app_date] => 2024-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18671202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/671202
VECTOR COMPUTATION APPARATUS, PROCESSOR, SYSTEM ON CHIP AND ELECTRONIC DEVICE May 21, 2024 Abandoned
Array ( [id] => 20351463 [patent_doc_number] => 20250348315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => Multi-Instruction Packing In Single Instruction Slot [patent_app_type] => utility [patent_app_number] => 18/660925 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660925 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660925
Multi-Instruction Packing In Single Instruction Slot May 9, 2024 Pending
Array ( [id] => 19419928 [patent_doc_number] => 20240296051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION [patent_app_type] => utility [patent_app_number] => 18/661103 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661103 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661103
APPARATUSES AND METHODS FOR SPECULATIVE EXECUTION SIDE CHANNEL MITIGATION May 9, 2024 Pending
Array ( [id] => 19391385 [patent_doc_number] => 20240281255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SUPER-THREAD PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/649817 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18649817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/649817
SUPER-THREAD PROCESSOR Apr 28, 2024 Pending
Array ( [id] => 19391381 [patent_doc_number] => 20240281251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => INSTRUCTION LENGTH BASED PARALLEL INSTRUCTION DEMARCATOR [patent_app_type] => utility [patent_app_number] => 18/648259 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648259 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648259
INSTRUCTION LENGTH BASED PARALLEL INSTRUCTION DEMARCATOR Apr 25, 2024 Pending
Array ( [id] => 19334292 [patent_doc_number] => 20240248722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO REQUEST A HISTORY RESET OF A PROCESSOR CORE [patent_app_type] => utility [patent_app_number] => 18/626629 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626629 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626629
Apparatuses, methods, and systems for instructions to request a history reset of a processor core Apr 3, 2024 Issued
Array ( [id] => 20790075 [patent_doc_number] => 12663990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Apparatus and method for remote atomic floating point operations [patent_app_type] => utility [patent_app_number] => 18/621071 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 15916 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621071 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621071
Apparatus and method for remote atomic floating point operations Mar 27, 2024 Issued
Array ( [id] => 19963801 [patent_doc_number] => 12333310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Base plus offset addressing for load/store messages [patent_app_type] => utility [patent_app_number] => 18/620217 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 57 [patent_no_of_words] => 44293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620217 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620217
Base plus offset addressing for load/store messages Mar 27, 2024 Issued
Array ( [id] => 19481956 [patent_doc_number] => 20240329998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => WAVE LEVEL MATRIX MULTIPLY INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/619392 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619392 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619392
WAVE LEVEL MATRIX MULTIPLY INSTRUCTIONS Mar 27, 2024 Pending
Array ( [id] => 20145583 [patent_doc_number] => 12379925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Exposing valid byte lanes as vector predicates to CPU [patent_app_type] => utility [patent_app_number] => 18/614947 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 21689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614947 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614947
Exposing valid byte lanes as vector predicates to CPU Mar 24, 2024 Issued
Array ( [id] => 20208553 [patent_doc_number] => 20250278273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => ASYNCHRONOUS RELEASE OPERATIONS IN A MULTIPROCESSOR SYSTEM [patent_app_type] => utility [patent_app_number] => 18/593817 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/593817
Asynchronous release operations in a multiprocessor system Feb 29, 2024 Issued
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