Search

Octavia L. Davis-hollington

Examiner (ID: 12421, Phone: (571)272-2176 , Office: P/2855 )

Most Active Art Unit
2855
Art Unit(s)
2856, 2855
Total Applications
1929
Issued Applications
1579
Pending Applications
125
Abandoned Applications
245

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11795715 [patent_doc_number] => 09405539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-02 [patent_title] => 'Providing vector sub-byte decompression functionality' [patent_app_type] => utility [patent_app_number] => 13/956347 [patent_app_country] => US [patent_app_date] => 2013-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 27437 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13956347 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/956347
Providing vector sub-byte decompression functionality Jul 30, 2013 Issued
13/982854 INTEGRATED CIRCUIT DEVICES AND METHODS FOR INSTRUCTION SCHEDULING AND EXECUTING A RESTRICTED LOAD OPERATION SPECULATIVELY SCHEDULED AHEAD OF A SCHEDULING RESTRICTION Jul 30, 2013 Abandoned
Array ( [id] => 9540201 [patent_doc_number] => 20140164848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'TRACING INSTRUCTION POINTERS AND DATA ACCESSES' [patent_app_type] => utility [patent_app_number] => 13/898065 [patent_app_country] => US [patent_app_date] => 2013-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13898065 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/898065
TRACING INSTRUCTION POINTERS AND DATA ACCESSES May 19, 2013 Abandoned
Array ( [id] => 9123471 [patent_doc_number] => 20130290392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION' [patent_app_type] => utility [patent_app_number] => 13/844366 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12164 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13844366 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/844366
INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION Mar 14, 2013 Abandoned
Array ( [id] => 9017354 [patent_doc_number] => 20130232318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA' [patent_app_type] => utility [patent_app_number] => 13/844111 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6357 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13844111 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/844111
Methods, apparatus, and instructions for converting vector data Mar 14, 2013 Issued
Array ( [id] => 8978930 [patent_doc_number] => 20130212360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'In-Lane Vector Shuffle Instructions' [patent_app_type] => utility [patent_app_number] => 13/838048 [patent_app_country] => US [patent_app_date] => 2013-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5218 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13838048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/838048
Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bits Mar 14, 2013 Issued
Array ( [id] => 9150437 [patent_doc_number] => 20130304960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'Apparatus, System and Method For Configuration of Adaptive Integrated Circuitry Having Fixed, Application Specific Computational Elements' [patent_app_type] => utility [patent_app_number] => 13/799393 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12200 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13799393 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/799393
Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements Mar 12, 2013 Issued
Array ( [id] => 8952708 [patent_doc_number] => 20130198488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-01 [patent_title] => 'INTERCONNECTION NETWORK CONNECTING OPERATION-CONFIGURABLE NODES ACCORDING TO ONE OR MORE LEVELS OF ADJACENCY IN MULTIPLE DIMENSIONS OF COMMUNICATION IN A MULTI-PROCESSOR AND A NEURAL PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/792039 [patent_app_country] => US [patent_app_date] => 2013-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 26528 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13792039 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/792039
Methods and apparatus for creating and executing a packet of instructions organized according to data dependencies between adjacent instructions and utilizing networks based on adjacencies to transport data in response to execution of the instructions Mar 8, 2013 Issued
Array ( [id] => 9224945 [patent_doc_number] => 20140019720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA' [patent_app_type] => utility [patent_app_number] => 13/762220 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6344 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762220 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762220
METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA Feb 6, 2013 Abandoned
Array ( [id] => 8843532 [patent_doc_number] => 20130139160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'SYSTEM AND METHOD FOR AUTOMATIC STORAGE LOAD BALANCING IN VIRTUAL SERVER ENVIRONMENTS' [patent_app_type] => utility [patent_app_number] => 13/749504 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12406 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13749504 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/749504
System and method for automatic storage load balancing in virtual server environments Jan 23, 2013 Issued
Array ( [id] => 8823778 [patent_doc_number] => 20130124823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'METHODS, APPARATUS, AND INSTRUCTIONS FOR PROCESSING VECTOR DATA' [patent_app_type] => utility [patent_app_number] => 13/736077 [patent_app_country] => US [patent_app_date] => 2013-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5151 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13736077 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/736077
METHODS, APPARATUS, AND INSTRUCTIONS FOR PROCESSING VECTOR DATA Jan 7, 2013 Abandoned
Array ( [id] => 12249058 [patent_doc_number] => 09921832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Instruction to reduce elements in a vector register with strided access pattern' [patent_app_type] => utility [patent_app_number] => 13/993653 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 9234 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993653 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993653
Instruction to reduce elements in a vector register with strided access pattern Dec 27, 2012 Issued
Array ( [id] => 9571589 [patent_doc_number] => 20140189302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'OPTIMAL LOGICAL PROCESSOR COUNT AND TYPE SELECTION FOR A GIVEN WORKLOAD BASED ON PLATFORM THERMALS AND POWER BUDGETING CONSTRAINTS' [patent_app_type] => utility [patent_app_number] => 13/993547 [patent_app_country] => US [patent_app_date] => 2012-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13993547 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/993547
OPTIMAL LOGICAL PROCESSOR COUNT AND TYPE SELECTION FOR A GIVEN WORKLOAD BASED ON PLATFORM THERMALS AND POWER BUDGETING CONSTRAINTS Dec 27, 2012 Abandoned
Array ( [id] => 10596195 [patent_doc_number] => 09317283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Running shift for divide instructions for processing vectors' [patent_app_type] => utility [patent_app_number] => 13/717480 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 10465 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13717480 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/717480
Running shift for divide instructions for processing vectors Dec 16, 2012 Issued
Array ( [id] => 9520483 [patent_doc_number] => 20140156975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'Redundant Threading for Improved Reliability' [patent_app_type] => utility [patent_app_number] => 13/690841 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6990 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690841 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/690841
Redundant Threading for Improved Reliability Nov 29, 2012 Abandoned
Array ( [id] => 8735176 [patent_doc_number] => 20130080745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'FINE-GRAINED INSTRUCTION ENABLEMENT AT SUB-FUNCTION GRANULARITY' [patent_app_type] => utility [patent_app_number] => 13/681520 [patent_app_country] => US [patent_app_date] => 2012-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14833 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13681520 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/681520
Fine-grained instruction enablement at sub-function granularity based on an indicated subrange of registers Nov 19, 2012 Issued
Array ( [id] => 8735469 [patent_doc_number] => 20130081038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'MULTIPROCESSOR COMPUTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/680369 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3454 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680369 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680369
MULTIPROCESSOR COMPUTING DEVICE Nov 18, 2012 Abandoned
Array ( [id] => 9465380 [patent_doc_number] => 20140129807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'APPROACH FOR EFFICIENT ARITHMETIC OPERATIONS' [patent_app_type] => utility [patent_app_number] => 13/671485 [patent_app_country] => US [patent_app_date] => 2012-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671485 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671485
Providing hints to an execution unit to prepare for predicted subsequent arithmetic operations Nov 6, 2012 Issued
Array ( [id] => 9578813 [patent_doc_number] => 08769249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Instructions with floating point control override' [patent_app_type] => utility [patent_app_number] => 13/670326 [patent_app_country] => US [patent_app_date] => 2012-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4714 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670326 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/670326
Instructions with floating point control override Nov 5, 2012 Issued
Array ( [id] => 9398408 [patent_doc_number] => 20140095814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'Memory Renaming Mechanism in Microarchitecture' [patent_app_type] => utility [patent_app_number] => 13/631644 [patent_app_country] => US [patent_app_date] => 2012-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5140 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13631644 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/631644
Memory Renaming Mechanism in Microarchitecture Sep 27, 2012 Abandoned
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