Octavian Rotaru

Array ( [id] => 19850346 [patent_doc_number] => 20250095697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => BANK TO BANK DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 18/959128 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18959128 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19834186 [patent_doc_number] => 20250085972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => METHOD AND TENSOR TRAVERSAL ENGINE FOR STRIDED MEMORY ACCESS DURING EXECUTION OF NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 18/957297 [patent_app_country] => US [patent_app_date] => 2024-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18957297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20035039 [patent_doc_number] => 20250173261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MEMORY DEVICE AND MEMORY SYSTEM FOR PERFORMING SWAP OPERATION [patent_app_type] => utility [patent_app_number] => 18/954847 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20446802 [patent_doc_number] => 20260003524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => COMPUTATIONAL STORAGE SYSTEM SUPPORTING MULTIPLE TOPOLOGIES AND METHOD OF OPERATION [patent_app_type] => utility [patent_app_number] => 18/954469 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3414 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19818920 [patent_doc_number] => 20250077127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => DATA STORAGE METHOD, STORAGE APPARATUS AND HOST [patent_app_type] => utility [patent_app_number] => 18/952134 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11757 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20123350 [patent_doc_number] => 20250238381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => DMA DEVICE, OPERATING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING DMA DEVICE [patent_app_type] => utility [patent_app_number] => 18/940052 [patent_app_country] => US [patent_app_date] => 2024-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18940052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19992517 [patent_doc_number] => 20250130739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => QUAD-DATA-RATE (QDR) HOST INTERFACE IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/935798 [patent_app_country] => US [patent_app_date] => 2024-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19771916 [patent_doc_number] => 20250053342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => COMPUTATIONAL STORAGE AND NETWORKED BASED SYSTEM [patent_app_type] => utility [patent_app_number] => 18/927374 [patent_app_country] => US [patent_app_date] => 2024-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18927374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19995495 [patent_doc_number] => 20250133717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => MEMORY DEVICE INCLUDING SEMICONDUCTOR ELEMENT [patent_app_type] => utility [patent_app_number] => 18/922784 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18922784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20018128 [patent_doc_number] => 20250156350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 18/920424 [patent_app_country] => US [patent_app_date] => 2024-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18920424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19748001 [patent_doc_number] => 20250036566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY PROCESSING UNIT ARCHITECTURE MAPPING TECHNIQUES [patent_app_type] => utility [patent_app_number] => 18/919260 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19748000 [patent_doc_number] => 20250036565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY PROCESSING UNIT CORE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/917509 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917509 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20380311 [patent_doc_number] => 20250362804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => DATA INPUT AND OUTPUT METHOD AND SEMICONDUCTOR DEVICE USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/915560 [patent_app_country] => US [patent_app_date] => 2024-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18915560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20196545 [patent_doc_number] => 20250273255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/910619 [patent_app_country] => US [patent_app_date] => 2024-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18910619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20052143 [patent_doc_number] => 20250190365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => DATA PADDING DEVICE AND DATA PADDING METHOD [patent_app_type] => utility [patent_app_number] => 18/895502 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18895502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20323005 [patent_doc_number] => 20250335093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => CONTROLLER AND MEMORY SYSTEM INCLUDING A MAILBOX [patent_app_type] => utility [patent_app_number] => 18/882762 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18882762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20623890 [patent_doc_number] => 12591397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Constructing virtual storage systems from a variety of components [patent_app_type] => utility [patent_app_number] => 18/821618 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 37 [patent_no_of_words] => 62194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19645418 [patent_doc_number] => 20240419938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => ALLOCATION SYSTEM IN HOSPITAL BY USING GRAPH DATA OF DOCTOR AND PATIENT [patent_app_type] => utility [patent_app_number] => 18/815926 [patent_app_country] => US [patent_app_date] => 2024-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20556878 [patent_doc_number] => 20260056662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => Buffers Configured for Individual Submission Queues in Communications between a Memory Sub-System and a Host System [patent_app_type] => utility [patent_app_number] => 18/814917 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18814917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20388023 [patent_doc_number] => 12487749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Flash memory controller, operating method of flash memory controller, and storage device capable of performing different dimension error correction to protect data [patent_app_type] => utility [patent_app_number] => 18/810487 [patent_app_country] => US [patent_app_date] => 2024-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18810487 [rel_patent_id] =>[rel_patent_doc_number] =>)