Search

Octavian Rotaru

Examiner (ID: 9637, Phone: (571)270-7950 , Office: P/3624 )

Most Active Art Unit
3624
Art Unit(s)
3624
Total Applications
478
Issued Applications
123
Pending Applications
75
Abandoned Applications
289

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13830623 [patent_doc_number] => 20190018796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => METHOD AND APPARATUS FOR AN EFFICIENT TLB LOOKUP [patent_app_type] => utility [patent_app_number] => 15/843933 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843933 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/843933
Method and apparatus for an efficient TLB lookup Dec 14, 2017 Issued
Array ( [id] => 12665953 [patent_doc_number] => 20180113817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => VIRTUALIZATION-BASED PLATFORM PROTECTION TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 15/839331 [patent_app_country] => US [patent_app_date] => 2017-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15839331 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/839331
Virtualization-based platform protection technology Dec 11, 2017 Issued
Array ( [id] => 13540661 [patent_doc_number] => 20180321877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => EXTENDING DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/811700 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811700 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811700
EXTENDING DEVICE AND MEMORY SYSTEM Nov 13, 2017 Abandoned
Array ( [id] => 13483295 [patent_doc_number] => 20180293190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => DATA STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/812110 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6103 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812110 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812110
Data storage device Nov 13, 2017 Issued
Array ( [id] => 13483239 [patent_doc_number] => 20180293162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => METHOD AND APPARATUS FOR PERFORMING MEMORY SPACE RESERVATION AND MANAGEMENT [patent_app_type] => utility [patent_app_number] => 15/811698 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811698 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/811698
Method and apparatus for performing memory space reservation and management Nov 13, 2017 Issued
Array ( [id] => 15638341 [patent_doc_number] => 10592164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Portions of configuration state registers in-memory [patent_app_type] => utility [patent_app_number] => 15/812277 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 51 [patent_no_of_words] => 25842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812277 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812277
Portions of configuration state registers in-memory Nov 13, 2017 Issued
Array ( [id] => 15486035 [patent_doc_number] => 10558366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-11 [patent_title] => Automatic pinning of units of memory [patent_app_type] => utility [patent_app_number] => 15/812228 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 51 [patent_no_of_words] => 25969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15812228 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/812228
Automatic pinning of units of memory Nov 13, 2017 Issued
Array ( [id] => 12221874 [patent_doc_number] => 20180060234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/806217 [patent_app_country] => US [patent_app_date] => 2017-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15147 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15806217 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/806217
Multiple data channel memory module architecture Nov 6, 2017 Issued
Array ( [id] => 12241841 [patent_doc_number] => 20180074704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'MEMORY CONTROLLER ARCHITECTURE WITH IMPROVED MEMORY SCHEDULING EFFICIENCY' [patent_app_type] => utility [patent_app_number] => 15/804930 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11540 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804930 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804930
Memory controller architecture with improved memory scheduling efficiency Nov 5, 2017 Issued
Array ( [id] => 12207545 [patent_doc_number] => 20180052771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'ADAPTIVELY ENABLING AND DISABLING SNOOPING BUS COMMANDS' [patent_app_type] => utility [patent_app_number] => 15/796507 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796507 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/796507
Adaptively enabling and disabling snooping bus commands Oct 26, 2017 Issued
Array ( [id] => 12140185 [patent_doc_number] => 20180018268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'PROVIDING MEMORY BANDWIDTH COMPRESSION USING MULTIPLE LAST-LEVEL CACHE (LLC) LINES IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/718449 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11497 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718449
Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system Sep 27, 2017 Issued
Array ( [id] => 12140185 [patent_doc_number] => 20180018268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'PROVIDING MEMORY BANDWIDTH COMPRESSION USING MULTIPLE LAST-LEVEL CACHE (LLC) LINES IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/718449 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11497 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718449
Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system Sep 27, 2017 Issued
Array ( [id] => 12140185 [patent_doc_number] => 20180018268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'PROVIDING MEMORY BANDWIDTH COMPRESSION USING MULTIPLE LAST-LEVEL CACHE (LLC) LINES IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/718449 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11497 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718449
Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system Sep 27, 2017 Issued
Array ( [id] => 12140039 [patent_doc_number] => 20180018122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'PROVIDING MEMORY BANDWIDTH COMPRESSION USING COMPRESSION INDICATOR (CI) HINT DIRECTORIES IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/718515 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12706 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718515 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718515
Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system Sep 27, 2017 Issued
Array ( [id] => 12140185 [patent_doc_number] => 20180018268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-18 [patent_title] => 'PROVIDING MEMORY BANDWIDTH COMPRESSION USING MULTIPLE LAST-LEVEL CACHE (LLC) LINES IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/718449 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11497 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718449 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/718449
Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system Sep 27, 2017 Issued
Array ( [id] => 16494453 [patent_doc_number] => 10860495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Storage circuitry responsive to a tag-matching command [patent_app_type] => utility [patent_app_number] => 16/464019 [patent_app_country] => US [patent_app_date] => 2017-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 8506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16464019 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/464019
Storage circuitry responsive to a tag-matching command Sep 14, 2017 Issued
Array ( [id] => 13240605 [patent_doc_number] => 10133501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => Data generating apparatus, data generating method, and data recording system [patent_app_type] => utility [patent_app_number] => 15/703286 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 12741 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703286 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703286
Data generating apparatus, data generating method, and data recording system Sep 12, 2017 Issued
Array ( [id] => 14047505 [patent_doc_number] => 20190079859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => APPARATUS, COMPUTER PROGRAM PRODUCT, SYSTEM, AND METHOD FOR MANAGING MULTIPLE REGIONS OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/703907 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703907 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703907
Apparatus, computer program product, system, and method for managing multiple regions of a memory device Sep 12, 2017 Issued
Array ( [id] => 14917571 [patent_doc_number] => 10430105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Storage scheme for a distributed storage system [patent_app_type] => utility [patent_app_number] => 15/703719 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9386 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703719 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703719
Storage scheme for a distributed storage system Sep 12, 2017 Issued
Array ( [id] => 14047135 [patent_doc_number] => 20190079674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => Storage Scheme for a Distributed Storage System [patent_app_type] => utility [patent_app_number] => 15/703790 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703790
Storage scheme for a distributed storage system Sep 12, 2017 Issued
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