Search

Octavian Rotaru

Examiner (ID: 9637, Phone: (571)270-7950 , Office: P/3624 )

Most Active Art Unit
3624
Art Unit(s)
3624
Total Applications
478
Issued Applications
123
Pending Applications
75
Abandoned Applications
289

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9314847 [patent_doc_number] => 08656082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Flexible and expandable memory architectures' [patent_app_type] => utility [patent_app_number] => 12/186357 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 5955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12186357 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186357
Flexible and expandable memory architectures Aug 4, 2008 Issued
Array ( [id] => 6262522 [patent_doc_number] => 20100030967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'METHOD AND SYSTEM FOR SECURING INSTRUCTION CACHES USING SUBSTANTIALLY RANDOM INSTRUCTION MAPPING SCHEME' [patent_app_type] => utility [patent_app_number] => 12/183689 [patent_app_country] => US [patent_app_date] => 2008-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3668 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20100030967.pdf [firstpage_image] =>[orig_patent_app_number] => 12183689 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/183689
Method and system for securing instruction caches using substantially random instruction mapping scheme Jul 30, 2008 Issued
Array ( [id] => 4641912 [patent_doc_number] => 08019946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Method and system for securing instruction caches using cache line locking' [patent_app_type] => utility [patent_app_number] => 12/183908 [patent_app_country] => US [patent_app_date] => 2008-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 3978 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019946.pdf [firstpage_image] =>[orig_patent_app_number] => 12183908 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/183908
Method and system for securing instruction caches using cache line locking Jul 30, 2008 Issued
Array ( [id] => 6262624 [patent_doc_number] => 20100030992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'INITIALIZING OF A MEMORY AREA' [patent_app_type] => utility [patent_app_number] => 12/182045 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3985 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20100030992.pdf [firstpage_image] =>[orig_patent_app_number] => 12182045 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/182045
Initializing of a memory area Jul 28, 2008 Issued
Array ( [id] => 7517818 [patent_doc_number] => 08041899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'System and method for fetching information to a cache module using a write back allocate algorithm' [patent_app_type] => utility [patent_app_number] => 12/181701 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4020 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/041/08041899.pdf [firstpage_image] =>[orig_patent_app_number] => 12181701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/181701
System and method for fetching information to a cache module using a write back allocate algorithm Jul 28, 2008 Issued
Array ( [id] => 4838351 [patent_doc_number] => 20080278836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'Testing Data Transfer Time of Disk Drives in Consumer Electronics Devices' [patent_app_type] => utility [patent_app_number] => 12/178718 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20080278836.pdf [firstpage_image] =>[orig_patent_app_number] => 12178718 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/178718
Testing data transfer time of disk drives in consumer electronics devices Jul 23, 2008 Issued
Array ( [id] => 8259972 [patent_doc_number] => 08209486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Cache memory' [patent_app_type] => utility [patent_app_number] => 12/217119 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4185 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12217119 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/217119
Cache memory Jun 30, 2008 Issued
Array ( [id] => 6639784 [patent_doc_number] => 20100005269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'Translation of virtual to physical addresses' [patent_app_type] => utility [patent_app_number] => 12/216253 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20100005269.pdf [firstpage_image] =>[orig_patent_app_number] => 12216253 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/216253
Translation of virtual to physical addresses Jun 30, 2008 Issued
Array ( [id] => 4641919 [patent_doc_number] => 08019953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Method for providing atomicity for host write input/outputs (I/Os) in a continuous data protection (CDP)-enabled volume using intent log' [patent_app_type] => utility [patent_app_number] => 12/217201 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4043 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/019/08019953.pdf [firstpage_image] =>[orig_patent_app_number] => 12217201 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/217201
Method for providing atomicity for host write input/outputs (I/Os) in a continuous data protection (CDP)-enabled volume using intent log Jun 30, 2008 Issued
Array ( [id] => 5467400 [patent_doc_number] => 20090327600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'OPTIMIZED CACHE COHERENCY IN A DUAL-CONTROLLER STORAGE ARRAY' [patent_app_type] => utility [patent_app_number] => 12/165181 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2692 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20090327600.pdf [firstpage_image] =>[orig_patent_app_number] => 12165181 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165181
Optimized cache coherency in a dual-controller storage array Jun 29, 2008 Issued
Array ( [id] => 6005970 [patent_doc_number] => 20110119425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/675105 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13314 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119425.pdf [firstpage_image] =>[orig_patent_app_number] => 12675105 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/675105
DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM Jun 29, 2008 Abandoned
Array ( [id] => 4591902 [patent_doc_number] => 07836246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device' [patent_app_type] => utility [patent_app_number] => 12/214952 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 9475 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836246.pdf [firstpage_image] =>[orig_patent_app_number] => 12214952 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/214952
Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device Jun 22, 2008 Issued
Array ( [id] => 4539831 [patent_doc_number] => 07953951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Systems and methods for time division multiplex multithreading' [patent_app_type] => utility [patent_app_number] => 12/124396 [patent_app_country] => US [patent_app_date] => 2008-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5496 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/953/07953951.pdf [firstpage_image] =>[orig_patent_app_number] => 12124396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/124396
Systems and methods for time division multiplex multithreading May 20, 2008 Issued
Array ( [id] => 5497493 [patent_doc_number] => 20090265521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'PATTERN PROTECTION METHOD AND CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/105743 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3556 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20090265521.pdf [firstpage_image] =>[orig_patent_app_number] => 12105743 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105743
PATTERN PROTECTION METHOD AND CIRCUIT Apr 17, 2008 Abandoned
Array ( [id] => 4815189 [patent_doc_number] => 20080195820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'PREFETCH MISS INDICATOR FOR CACHE COHERENCE DIRECTORY MISSES ON EXTERNAL CACHES' [patent_app_type] => utility [patent_app_number] => 12/105405 [patent_app_country] => US [patent_app_date] => 2008-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4594 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20080195820.pdf [firstpage_image] =>[orig_patent_app_number] => 12105405 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/105405
Prefetch miss indicator for cache coherence directory misses on external caches Apr 17, 2008 Issued
Array ( [id] => 4888970 [patent_doc_number] => 20080263302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Non-volatile memory circuit, system, and method' [patent_app_type] => utility [patent_app_number] => 12/148521 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6550 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263302.pdf [firstpage_image] =>[orig_patent_app_number] => 12148521 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/148521
Non-volatile memory circuit, system, and method Apr 16, 2008 Issued
Array ( [id] => 8259985 [patent_doc_number] => 08209493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Systems and methods for scheduling memory requests during memory throttling' [patent_app_type] => utility [patent_app_number] => 12/055417 [patent_app_country] => US [patent_app_date] => 2008-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4930 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12055417 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/055417
Systems and methods for scheduling memory requests during memory throttling Mar 25, 2008 Issued
Array ( [id] => 4825847 [patent_doc_number] => 20080229036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-18 [patent_title] => 'Information Processing apparatus and computer-readable storage medium' [patent_app_type] => utility [patent_app_number] => 12/071966 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7153 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20080229036.pdf [firstpage_image] =>[orig_patent_app_number] => 12071966 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/071966
Information processing apparatus and computer-readable storage medium Feb 27, 2008 Issued
Array ( [id] => 8530595 [patent_doc_number] => 08307180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Extended utilization area for a memory device' [patent_app_type] => utility [patent_app_number] => 12/039672 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4393 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12039672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/039672
Extended utilization area for a memory device Feb 27, 2008 Issued
Array ( [id] => 5516633 [patent_doc_number] => 20090216940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'Method for accessing a first-in-first-out (FIFO) buffer and a FIFO controller therefor' [patent_app_type] => utility [patent_app_number] => 12/071828 [patent_app_country] => US [patent_app_date] => 2008-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20090216940.pdf [firstpage_image] =>[orig_patent_app_number] => 12071828 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/071828
Method for accessing a first-in-first-out (FIFO) buffer and a FIFO controller therefor Feb 26, 2008 Issued
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