
Octavian Rotaru
Examiner (ID: 9637, Phone: (571)270-7950 , Office: P/3624 )
| Most Active Art Unit | 3624 |
| Art Unit(s) | 3624 |
| Total Applications | 478 |
| Issued Applications | 123 |
| Pending Applications | 75 |
| Abandoned Applications | 289 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 9314847
[patent_doc_number] => 08656082
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-18
[patent_title] => 'Flexible and expandable memory architectures'
[patent_app_type] => utility
[patent_app_number] => 12/186357
[patent_app_country] => US
[patent_app_date] => 2008-08-05
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 5955
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12186357
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/186357 | Flexible and expandable memory architectures | Aug 4, 2008 | Issued |
Array
(
[id] => 6262522
[patent_doc_number] => 20100030967
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-04
[patent_title] => 'METHOD AND SYSTEM FOR SECURING INSTRUCTION CACHES USING SUBSTANTIALLY RANDOM INSTRUCTION MAPPING SCHEME'
[patent_app_type] => utility
[patent_app_number] => 12/183689
[patent_app_country] => US
[patent_app_date] => 2008-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 3668
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20100030967.pdf
[firstpage_image] =>[orig_patent_app_number] => 12183689
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/183689 | Method and system for securing instruction caches using substantially random instruction mapping scheme | Jul 30, 2008 | Issued |
Array
(
[id] => 4641912
[patent_doc_number] => 08019946
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-13
[patent_title] => 'Method and system for securing instruction caches using cache line locking'
[patent_app_type] => utility
[patent_app_number] => 12/183908
[patent_app_country] => US
[patent_app_date] => 2008-07-31
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[patent_drawing_sheets_cnt] => 11
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[pdf_file] => patents/08/019/08019946.pdf
[firstpage_image] =>[orig_patent_app_number] => 12183908
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/183908 | Method and system for securing instruction caches using cache line locking | Jul 30, 2008 | Issued |
Array
(
[id] => 6262624
[patent_doc_number] => 20100030992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-04
[patent_title] => 'INITIALIZING OF A MEMORY AREA'
[patent_app_type] => utility
[patent_app_number] => 12/182045
[patent_app_country] => US
[patent_app_date] => 2008-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[firstpage_image] =>[orig_patent_app_number] => 12182045
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/182045 | Initializing of a memory area | Jul 28, 2008 | Issued |
Array
(
[id] => 7517818
[patent_doc_number] => 08041899
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-18
[patent_title] => 'System and method for fetching information to a cache module using a write back allocate algorithm'
[patent_app_type] => utility
[patent_app_number] => 12/181701
[patent_app_country] => US
[patent_app_date] => 2008-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/08/041/08041899.pdf
[firstpage_image] =>[orig_patent_app_number] => 12181701
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/181701 | System and method for fetching information to a cache module using a write back allocate algorithm | Jul 28, 2008 | Issued |
Array
(
[id] => 4838351
[patent_doc_number] => 20080278836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-11-13
[patent_title] => 'Testing Data Transfer Time of Disk Drives in Consumer Electronics Devices'
[patent_app_type] => utility
[patent_app_number] => 12/178718
[patent_app_country] => US
[patent_app_date] => 2008-07-24
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[pdf_file] => publications/A1/0278/20080278836.pdf
[firstpage_image] =>[orig_patent_app_number] => 12178718
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/178718 | Testing data transfer time of disk drives in consumer electronics devices | Jul 23, 2008 | Issued |
Array
(
[id] => 8259972
[patent_doc_number] => 08209486
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-26
[patent_title] => 'Cache memory'
[patent_app_type] => utility
[patent_app_number] => 12/217119
[patent_app_country] => US
[patent_app_date] => 2008-07-01
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12217119
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/217119 | Cache memory | Jun 30, 2008 | Issued |
Array
(
[id] => 6639784
[patent_doc_number] => 20100005269
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-07
[patent_title] => 'Translation of virtual to physical addresses'
[patent_app_type] => utility
[patent_app_number] => 12/216253
[patent_app_country] => US
[patent_app_date] => 2008-07-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0005/20100005269.pdf
[firstpage_image] =>[orig_patent_app_number] => 12216253
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/216253 | Translation of virtual to physical addresses | Jun 30, 2008 | Issued |
Array
(
[id] => 4641919
[patent_doc_number] => 08019953
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-09-13
[patent_title] => 'Method for providing atomicity for host write input/outputs (I/Os) in a continuous data protection (CDP)-enabled volume using intent log'
[patent_app_type] => utility
[patent_app_number] => 12/217201
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[pdf_file] => patents/08/019/08019953.pdf
[firstpage_image] =>[orig_patent_app_number] => 12217201
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/217201 | Method for providing atomicity for host write input/outputs (I/Os) in a continuous data protection (CDP)-enabled volume using intent log | Jun 30, 2008 | Issued |
Array
(
[id] => 5467400
[patent_doc_number] => 20090327600
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-31
[patent_title] => 'OPTIMIZED CACHE COHERENCY IN A DUAL-CONTROLLER STORAGE ARRAY'
[patent_app_type] => utility
[patent_app_number] => 12/165181
[patent_app_country] => US
[patent_app_date] => 2008-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0327/20090327600.pdf
[firstpage_image] =>[orig_patent_app_number] => 12165181
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/165181 | Optimized cache coherency in a dual-controller storage array | Jun 29, 2008 | Issued |
Array
(
[id] => 6005970
[patent_doc_number] => 20110119425
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-05-19
[patent_title] => 'DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 12/675105
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[pdf_file] => publications/A1/0119/20110119425.pdf
[firstpage_image] =>[orig_patent_app_number] => 12675105
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/675105 | DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM | Jun 29, 2008 | Abandoned |
Array
(
[id] => 4591902
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[patent_issue_date] => 2010-11-16
[patent_title] => 'Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device'
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[patent_app_number] => 12/214952
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[pdf_file] => patents/07/836/07836246.pdf
[firstpage_image] =>[orig_patent_app_number] => 12214952
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/214952 | Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) device | Jun 22, 2008 | Issued |
Array
(
[id] => 4539831
[patent_doc_number] => 07953951
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-31
[patent_title] => 'Systems and methods for time division multiplex multithreading'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/124396 | Systems and methods for time division multiplex multithreading | May 20, 2008 | Issued |
Array
(
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[patent_title] => 'PATTERN PROTECTION METHOD AND CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/105743 | PATTERN PROTECTION METHOD AND CIRCUIT | Apr 17, 2008 | Abandoned |
Array
(
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[patent_title] => 'PREFETCH MISS INDICATOR FOR CACHE COHERENCE DIRECTORY MISSES ON EXTERNAL CACHES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/105405 | Prefetch miss indicator for cache coherence directory misses on external caches | Apr 17, 2008 | Issued |
Array
(
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[patent_title] => 'Non-volatile memory circuit, system, and method'
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Array
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Array
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Array
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Array
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