Search

Octavian Rotaru

Examiner (ID: 9637, Phone: (571)270-7950 , Office: P/3624 )

Most Active Art Unit
3624
Art Unit(s)
3624
Total Applications
478
Issued Applications
123
Pending Applications
75
Abandoned Applications
289

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4589495 [patent_doc_number] => 07861054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Method and system for controlling information of logical division in a storage controller' [patent_app_type] => utility [patent_app_number] => 10/978486 [patent_app_country] => US [patent_app_date] => 2004-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 9550 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861054.pdf [firstpage_image] =>[orig_patent_app_number] => 10978486 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/978486
Method and system for controlling information of logical division in a storage controller Nov 1, 2004 Issued
Array ( [id] => 6907075 [patent_doc_number] => 20050102470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Disk array device' [patent_app_type] => utility [patent_app_number] => 10/974955 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7142 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20050102470.pdf [firstpage_image] =>[orig_patent_app_number] => 10974955 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/974955
Disk array device Oct 27, 2004 Abandoned
Array ( [id] => 921992 [patent_doc_number] => 07325099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Method and apparatus to enable DRAM to support low-latency access via vertical caching' [patent_app_type] => utility [patent_app_number] => 10/974122 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5844 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325099.pdf [firstpage_image] =>[orig_patent_app_number] => 10974122 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/974122
Method and apparatus to enable DRAM to support low-latency access via vertical caching Oct 26, 2004 Issued
Array ( [id] => 206433 [patent_doc_number] => 07634625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Storage system and method for copying volumes by inspection of data security' [patent_app_type] => utility [patent_app_number] => 10/974457 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 16552 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/634/07634625.pdf [firstpage_image] =>[orig_patent_app_number] => 10974457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/974457
Storage system and method for copying volumes by inspection of data security Oct 25, 2004 Issued
Array ( [id] => 5744332 [patent_doc_number] => 20060090058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Method and data storage system for providing multiple partition support' [patent_app_type] => utility [patent_app_number] => 10/973485 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3702 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20060090058.pdf [firstpage_image] =>[orig_patent_app_number] => 10973485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973485
Method and data storage system for providing multiple partition support Oct 25, 2004 Abandoned
Array ( [id] => 7245023 [patent_doc_number] => 20050080937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Invalidating translation lookaside buffer entries in a virtual machine (VM) system' [patent_app_type] => utility [patent_app_number] => 10/973678 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6023 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20050080937.pdf [firstpage_image] =>[orig_patent_app_number] => 10973678 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973678
Invalidating translation lookaside buffer entries in a virtual machine (VM) system Oct 24, 2004 Issued
Array ( [id] => 8623222 [patent_doc_number] => 08356143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-15 [patent_title] => 'Prefetch mechanism for bus master memory access' [patent_app_type] => utility [patent_app_number] => 10/971608 [patent_app_country] => US [patent_app_date] => 2004-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9668 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10971608 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/971608
Prefetch mechanism for bus master memory access Oct 21, 2004 Issued
Array ( [id] => 7803685 [patent_doc_number] => 08131969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Updating system configuration information' [patent_app_type] => utility [patent_app_number] => 10/969648 [patent_app_country] => US [patent_app_date] => 2004-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5017 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/131/08131969.pdf [firstpage_image] =>[orig_patent_app_number] => 10969648 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/969648
Updating system configuration information Oct 19, 2004 Issued
Array ( [id] => 231443 [patent_doc_number] => 07603535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Low power consumption semiconductor memory device capable of selectively changing input/output data width and data input/output method' [patent_app_type] => utility [patent_app_number] => 10/959114 [patent_app_country] => US [patent_app_date] => 2004-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/603/07603535.pdf [firstpage_image] =>[orig_patent_app_number] => 10959114 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/959114
Low power consumption semiconductor memory device capable of selectively changing input/output data width and data input/output method Oct 6, 2004 Issued
Array ( [id] => 6917070 [patent_doc_number] => 20050094631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Memory using packet controller and memory' [patent_app_type] => utility [patent_app_number] => 10/948674 [patent_app_country] => US [patent_app_date] => 2004-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5138 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20050094631.pdf [firstpage_image] =>[orig_patent_app_number] => 10948674 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/948674
Memory using packet controller and memory Sep 23, 2004 Issued
Array ( [id] => 5830624 [patent_doc_number] => 20060064547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches' [patent_app_type] => utility [patent_app_number] => 10/950279 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4049 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20060064547.pdf [firstpage_image] =>[orig_patent_app_number] => 10950279 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950279
Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches Sep 22, 2004 Issued
Array ( [id] => 593260 [patent_doc_number] => 07461200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-02 [patent_title] => 'Method and apparatus for overlaying flat and tree based data sets onto content addressable memory (CAM) device' [patent_app_type] => utility [patent_app_number] => 10/950323 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 9426 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/461/07461200.pdf [firstpage_image] =>[orig_patent_app_number] => 10950323 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/950323
Method and apparatus for overlaying flat and tree based data sets onto content addressable memory (CAM) device Sep 22, 2004 Issued
Array ( [id] => 7052445 [patent_doc_number] => 20050188164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'System and method for memory management' [patent_app_type] => utility [patent_app_number] => 10/945093 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8651 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20050188164.pdf [firstpage_image] =>[orig_patent_app_number] => 10945093 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/945093
Realtime memory management via locking realtime threads and related data structures Sep 20, 2004 Issued
Array ( [id] => 4488231 [patent_doc_number] => 07908450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-15 [patent_title] => 'Memory management unit, code verifying apparatus, and code decrypting apparatus' [patent_app_type] => utility [patent_app_number] => 10/939342 [patent_app_country] => US [patent_app_date] => 2004-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8458 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/908/07908450.pdf [firstpage_image] =>[orig_patent_app_number] => 10939342 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/939342
Memory management unit, code verifying apparatus, and code decrypting apparatus Sep 13, 2004 Issued
Array ( [id] => 7071121 [patent_doc_number] => 20050246506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Information processing device, processor, processor control method, information processing device control method and cache memory' [patent_app_type] => utility [patent_app_number] => 10/937253 [patent_app_country] => US [patent_app_date] => 2004-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8029 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20050246506.pdf [firstpage_image] =>[orig_patent_app_number] => 10937253 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/937253
Information processing device, processor, processor control method, information processing device control method and cache memory Sep 9, 2004 Issued
Array ( [id] => 226776 [patent_doc_number] => 07606973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-20 [patent_title] => 'System and method for pervasive computing with a portable non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 10/935855 [patent_app_country] => US [patent_app_date] => 2004-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4985 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/606/07606973.pdf [firstpage_image] =>[orig_patent_app_number] => 10935855 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/935855
System and method for pervasive computing with a portable non-volatile memory device Sep 7, 2004 Issued
Array ( [id] => 882080 [patent_doc_number] => 07360035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Atomic read/write support in a multi-module memory configuration' [patent_app_type] => utility [patent_app_number] => 10/931705 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4362 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360035.pdf [firstpage_image] =>[orig_patent_app_number] => 10931705 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931705
Atomic read/write support in a multi-module memory configuration Aug 31, 2004 Issued
Array ( [id] => 7166823 [patent_doc_number] => 20050086450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Information processing apparatus and file management method' [patent_app_type] => utility [patent_app_number] => 10/929601 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9558 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20050086450.pdf [firstpage_image] =>[orig_patent_app_number] => 10929601 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929601
Information processing apparatus and file management method Aug 30, 2004 Abandoned
Array ( [id] => 5900655 [patent_doc_number] => 20060044926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Method and system for accessing performance parameters in memory devices' [patent_app_type] => utility [patent_app_number] => 10/927776 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4009 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20060044926.pdf [firstpage_image] =>[orig_patent_app_number] => 10927776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/927776
Method and system for accessing performance parameters in memory devices Aug 26, 2004 Abandoned
Array ( [id] => 5906694 [patent_doc_number] => 20060047883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Serially indexing a cache memory' [patent_app_type] => utility [patent_app_number] => 10/927682 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4216 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20060047883.pdf [firstpage_image] =>[orig_patent_app_number] => 10927682 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/927682
Serially indexing a cache memory Aug 26, 2004 Issued
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