Array
(
[id] => 7245357
[patent_doc_number] => 20050080985
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Data storage device'
[patent_app_type] => utility
[patent_app_number] => 10/480760
[patent_app_country] => US
[patent_app_date] => 2003-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 10439
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0080/20050080985.pdf
[firstpage_image] =>[orig_patent_app_number] => 10480760
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/480760 | Data storage apparatus detachably mounted to a host apparatus | Apr 13, 2003 | Issued |
Array
(
[id] => 825553
[patent_doc_number] => 07406567
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-07-29
[patent_title] => 'Algorithm to improve packet processing performance using existing caching schemes'
[patent_app_type] => utility
[patent_app_number] => 10/291894
[patent_app_country] => US
[patent_app_date] => 2002-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2244
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/406/07406567.pdf
[firstpage_image] =>[orig_patent_app_number] => 10291894
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/291894 | Algorithm to improve packet processing performance using existing caching schemes | Nov 7, 2002 | Issued |
Array
(
[id] => 118134
[patent_doc_number] => 07716442
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-11
[patent_title] => 'Interfacing processors with external memory supporting burst mode'
[patent_app_type] => utility
[patent_app_number] => 10/489800
[patent_app_country] => US
[patent_app_date] => 2002-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1547
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/716/07716442.pdf
[firstpage_image] =>[orig_patent_app_number] => 10489800
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/489800 | Interfacing processors with external memory supporting burst mode | Sep 16, 2002 | Issued |