Search

Olga Asinovsky

Examiner (ID: 11483)

Most Active Art Unit
1711
Art Unit(s)
1511, 1713, 1711, 1509, 1714, 1796
Total Applications
1415
Issued Applications
1074
Pending Applications
99
Abandoned Applications
242

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14873069 [patent_doc_number] => 20190286776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SYSTEM DESIGN USING ACCURATE PERFORMANCE MODELS [patent_app_type] => utility [patent_app_number] => 16/430415 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/430415
System design using accurate performance models Jun 2, 2019 Issued
Array ( [id] => 14751203 [patent_doc_number] => 20190258775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => SYSTEM AND METHOD OF ANALYZING INTEGRATED CIRCUIT IN CONSIDERATION OF A PROCESS VARIATION AND A SHIFT [patent_app_type] => utility [patent_app_number] => 16/404910 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404910 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404910
System and method of analyzing integrated circuit in consideration of a process variation and a shift May 6, 2019 Issued
Array ( [id] => 14751195 [patent_doc_number] => 20190258771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => CHECKING WAFER-LEVEL INTEGRATED DESIGNS FOR RULE COMPLIANCE [patent_app_type] => utility [patent_app_number] => 16/400434 [patent_app_country] => US [patent_app_date] => 2019-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16400434 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/400434
Checking wafer-level integrated designs for rule compliance Apr 30, 2019 Issued
Array ( [id] => 16393151 [patent_doc_number] => 20200334092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => SYSTEM AND METHOD FOR IDENTIFYING A CAUSE OF A FAILURE IN OPERATION OF A CHIP [patent_app_type] => utility [patent_app_number] => 16/385848 [patent_app_country] => US [patent_app_date] => 2019-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16385848 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/385848
SYSTEM AND METHOD FOR IDENTIFYING A CAUSE OF A FAILURE IN OPERATION OF A CHIP Apr 15, 2019 Abandoned
Array ( [id] => 16987204 [patent_doc_number] => 11074379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Multi-cycle latch tree synthesis [patent_app_type] => utility [patent_app_number] => 16/370948 [patent_app_country] => US [patent_app_date] => 2019-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 12221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370948
Multi-cycle latch tree synthesis Mar 29, 2019 Issued
Array ( [id] => 16346566 [patent_doc_number] => 20200311217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => METHOD AND SYSTEM FOR IMPLEMENTING MEMORY CHANGES IN DIGITAL INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/370276 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370276 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370276
METHOD AND SYSTEM FOR IMPLEMENTING MEMORY CHANGES IN DIGITAL INTEGRATED CIRCUITS Mar 28, 2019 Abandoned
Array ( [id] => 16927353 [patent_doc_number] => 11048839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Adaptive error correction in quantum computing [patent_app_type] => utility [patent_app_number] => 16/370062 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9930 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370062 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370062
Adaptive error correction in quantum computing Mar 28, 2019 Issued
Array ( [id] => 17352450 [patent_doc_number] => 11227089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => System and method for implementing functional logics of verification IP using state design pattern based FSMs [patent_app_type] => utility [patent_app_number] => 16/370615 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6428 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16370615 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/370615
System and method for implementing functional logics of verification IP using state design pattern based FSMs Mar 28, 2019 Issued
Array ( [id] => 17801599 [patent_doc_number] => 11415896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Dissection method for layout patterns in semiconductor device, optical proximity correction method including the same and method of manufacturing semiconductor device including the same [patent_app_type] => utility [patent_app_number] => 16/369932 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 11573 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369932
Dissection method for layout patterns in semiconductor device, optical proximity correction method including the same and method of manufacturing semiconductor device including the same Mar 28, 2019 Issued
Array ( [id] => 20143422 [patent_doc_number] => 12377747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Method to detect vehicle battery type before charge [patent_app_type] => utility [patent_app_number] => 17/279201 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5761 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17279201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/279201
Method to detect vehicle battery type before charge Mar 28, 2019 Issued
Array ( [id] => 16117045 [patent_doc_number] => 20200210545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => CONSTRUCTION OF STAGING TREES ON FULLY HIERARCHICAL VLSI CIRCUIT DESIGNS [patent_app_type] => utility [patent_app_number] => 16/237995 [patent_app_country] => US [patent_app_date] => 2019-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237995
CONSTRUCTION OF STAGING TREES ON FULLY HIERARCHICAL VLSI CIRCUIT DESIGNS Jan 1, 2019 Abandoned
Array ( [id] => 16117023 [patent_doc_number] => 20200210534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => INTEGRATED CIRCUITRY DEVELOPMENT SYSTEM, INTEGRATED CIRCUITRY DEVELOPMENT METHOD, AND INTEGRATED CIRCUITRY [patent_app_type] => utility [patent_app_number] => 16/236758 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236758
INTEGRATED CIRCUITRY DEVELOPMENT SYSTEM, INTEGRATED CIRCUITRY DEVELOPMENT METHOD, AND INTEGRATED CIRCUITRY Dec 30, 2018 Abandoned
Array ( [id] => 15137473 [patent_doc_number] => 10482208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Coding and synthesizing a state machine in state groups [patent_app_type] => utility [patent_app_number] => 16/237657 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 10628 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237657 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237657
Coding and synthesizing a state machine in state groups Dec 30, 2018 Issued
Array ( [id] => 15623291 [patent_doc_number] => 20200082050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => FAILSAFE CIRCUIT, LAYOUT, DEVICE, AND METHOD [patent_app_type] => utility [patent_app_number] => 16/237165 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237165 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237165
Failsafe circuit, layout, device, and method Dec 30, 2018 Issued
Array ( [id] => 16117025 [patent_doc_number] => 20200210535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => METHOD AND SYSTEM FOR AUTOMATED DESIGN AND DESIGN-SPACE EXPLORATION [patent_app_type] => utility [patent_app_number] => 16/237429 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237429 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237429
Method and system for automated design and design-space exploration Dec 30, 2018 Issued
Array ( [id] => 16117043 [patent_doc_number] => 20200210544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SYSTEM AND METHOD FOR REDUCING SILICON AREA OF RESILIENT SYSTEMS USING FUNCTIONAL AND DUPLICATE LOGIC [patent_app_type] => utility [patent_app_number] => 16/236350 [patent_app_country] => US [patent_app_date] => 2018-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16236350 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/236350
SYSTEM AND METHOD FOR REDUCING SILICON AREA OF RESILIENT SYSTEMS USING FUNCTIONAL AND DUPLICATE LOGIC Dec 28, 2018 Abandoned
Array ( [id] => 15426301 [patent_doc_number] => 10546080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-28 [patent_title] => Method and system for identifying potential causes of failure in simulation runs using machine learning [patent_app_type] => utility [patent_app_number] => 16/233590 [patent_app_country] => US [patent_app_date] => 2018-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16233590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/233590
Method and system for identifying potential causes of failure in simulation runs using machine learning Dec 26, 2018 Issued
Array ( [id] => 16494714 [patent_doc_number] => 10860757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-08 [patent_title] => Multicorner skew scheduling circuit design [patent_app_type] => utility [patent_app_number] => 16/232794 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232794 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/232794
Multicorner skew scheduling circuit design Dec 25, 2018 Issued
Array ( [id] => 14539739 [patent_doc_number] => 20190205491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => METHOD AND APPARATUS OF EMULATION TECHNIQUES FOR ENHANCED FPGA VALIDATION [patent_app_type] => utility [patent_app_number] => 16/232583 [patent_app_country] => US [patent_app_date] => 2018-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16232583 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/232583
METHOD AND APPARATUS OF EMULATION TECHNIQUES FOR ENHANCED FPGA VALIDATION Dec 25, 2018 Abandoned
Array ( [id] => 14509115 [patent_doc_number] => 20190198212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => PERSONAL ELECTRONIC DEVICE CASE AND MOUNTING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/227663 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227663
PERSONAL ELECTRONIC DEVICE CASE AND MOUNTING SYSTEM Dec 19, 2018 Abandoned
Menu