Search

Olik Chaudhuri

Supervisory Patent Examiner (ID: 4041, Phone: (571)272-9820 , Office: P/2823 )

Most Active Art Unit
1104
Art Unit(s)
1104, 2823, 2814, 1106, 1107
Total Applications
949
Issued Applications
761
Pending Applications
4
Abandoned Applications
184

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2586452 [patent_doc_number] => 04908333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-13 [patent_title] => 'Process for manufacturing a semiconductor device having a contact window defined by an inclined surface of a composite film' [patent_app_type] => 1 [patent_app_number] => 7/168315 [patent_app_country] => US [patent_app_date] => 1988-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1978 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/908/04908333.pdf [firstpage_image] =>[orig_patent_app_number] => 168315 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/168315
Process for manufacturing a semiconductor device having a contact window defined by an inclined surface of a composite film Mar 16, 1988 Issued
Array ( [id] => 2540419 [patent_doc_number] => 04810357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-07 [patent_title] => 'Catalytic dewaxing of light and heavy oils in dual parallel reactors' [patent_app_type] => 1 [patent_app_number] => 7/171209 [patent_app_country] => US [patent_app_date] => 1988-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8092 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 410 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/810/04810357.pdf [firstpage_image] =>[orig_patent_app_number] => 171209 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/171209
Catalytic dewaxing of light and heavy oils in dual parallel reactors Mar 15, 1988 Issued
07/170569 SELF-ALIGNED ANTIBLOOMING STRUCTURE FOR CHARGE-COUPLED DEVICES AND METHOD OF FABRICATION THEREOF Mar 13, 1988 Abandoned
Array ( [id] => 2625933 [patent_doc_number] => 04920087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-24 [patent_title] => 'Vanadium scavenging compositions' [patent_app_type] => 1 [patent_app_number] => 7/165696 [patent_app_country] => US [patent_app_date] => 1988-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4231 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/920/04920087.pdf [firstpage_image] =>[orig_patent_app_number] => 165696 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/165696
Vanadium scavenging compositions Mar 8, 1988 Issued
Array ( [id] => 2478064 [patent_doc_number] => 04876216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-24 [patent_title] => 'Semiconductor integrated circuit manufacturing process providing oxide-filled trench isolation of circuit devices' [patent_app_type] => 1 [patent_app_number] => 7/164556 [patent_app_country] => US [patent_app_date] => 1988-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3108 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/876/04876216.pdf [firstpage_image] =>[orig_patent_app_number] => 164556 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/164556
Semiconductor integrated circuit manufacturing process providing oxide-filled trench isolation of circuit devices Mar 6, 1988 Issued
07/159818 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, IN WHICH A SILICON WAFER IS LOCALLY PROVIDED WITH FIELD OXIDE REGIONS Feb 23, 1988 Abandoned
Array ( [id] => 2563527 [patent_doc_number] => 04945066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-31 [patent_title] => 'Process for manufacturing a dynamic random access memory cell' [patent_app_type] => 1 [patent_app_number] => 7/159177 [patent_app_country] => US [patent_app_date] => 1988-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3061 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/945/04945066.pdf [firstpage_image] =>[orig_patent_app_number] => 159177 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/159177
Process for manufacturing a dynamic random access memory cell Feb 22, 1988 Issued
Array ( [id] => 2546072 [patent_doc_number] => 04804633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-02-14 [patent_title] => 'Silicon-on-insulator substrates annealed in polysilicon tube' [patent_app_type] => 1 [patent_app_number] => 7/157022 [patent_app_country] => US [patent_app_date] => 1988-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2331 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/804/04804633.pdf [firstpage_image] =>[orig_patent_app_number] => 157022 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/157022
Silicon-on-insulator substrates annealed in polysilicon tube Feb 17, 1988 Issued
Array ( [id] => 2484209 [patent_doc_number] => 04820653 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-11 [patent_title] => 'Technique for fabricating complementary dielectrically isolated wafer' [patent_app_type] => 1 [patent_app_number] => 7/155409 [patent_app_country] => US [patent_app_date] => 1988-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2056 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/820/04820653.pdf [firstpage_image] =>[orig_patent_app_number] => 155409 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/155409
Technique for fabricating complementary dielectrically isolated wafer Feb 11, 1988 Issued
Array ( [id] => 2486060 [patent_doc_number] => 04800172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-01-24 [patent_title] => 'Manufacturing method for cascaded junction field effect transistor' [patent_app_type] => 1 [patent_app_number] => 7/152396 [patent_app_country] => US [patent_app_date] => 1988-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3795 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/800/04800172.pdf [firstpage_image] =>[orig_patent_app_number] => 152396 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/152396
Manufacturing method for cascaded junction field effect transistor Feb 3, 1988 Issued
Array ( [id] => 2511198 [patent_doc_number] => 04851361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-25 [patent_title] => 'Fabrication process for EEPROMS with high voltage transistors' [patent_app_type] => 1 [patent_app_number] => 7/152313 [patent_app_country] => US [patent_app_date] => 1988-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 6116 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/851/04851361.pdf [firstpage_image] =>[orig_patent_app_number] => 152313 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/152313
Fabrication process for EEPROMS with high voltage transistors Feb 3, 1988 Issued
07/151555 IC WITH MEANS FOR REDUCING ESD DAMAGE Feb 1, 1988 Abandoned
Array ( [id] => 2586302 [patent_doc_number] => 04963500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-16 [patent_title] => 'Method of monitoring semiconductor manufacturing processes and test sample therefor' [patent_app_type] => 1 [patent_app_number] => 7/151436 [patent_app_country] => US [patent_app_date] => 1988-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2802 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/963/04963500.pdf [firstpage_image] =>[orig_patent_app_number] => 151436 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/151436
Method of monitoring semiconductor manufacturing processes and test sample therefor Feb 1, 1988 Issued
Array ( [id] => 2600957 [patent_doc_number] => 04912053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-27 [patent_title] => 'Ion implanted JFET with self-aligned source and drain' [patent_app_type] => 1 [patent_app_number] => 7/151184 [patent_app_country] => US [patent_app_date] => 1988-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 5170 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/912/04912053.pdf [firstpage_image] =>[orig_patent_app_number] => 151184 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/151184
Ion implanted JFET with self-aligned source and drain Jan 31, 1988 Issued
Array ( [id] => 2586221 [patent_doc_number] => 04891333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-02 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 7/150499 [patent_app_country] => US [patent_app_date] => 1988-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2482 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/891/04891333.pdf [firstpage_image] =>[orig_patent_app_number] => 150499 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/150499
Semiconductor device and manufacturing method thereof Jan 31, 1988 Issued
Array ( [id] => 2666525 [patent_doc_number] => 04904610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-27 [patent_title] => 'Wafer level process for fabricating passivated semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/143916 [patent_app_country] => US [patent_app_date] => 1988-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3481 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/904/04904610.pdf [firstpage_image] =>[orig_patent_app_number] => 143916 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/143916
Wafer level process for fabricating passivated semiconductor devices Jan 26, 1988 Issued
Array ( [id] => 2586177 [patent_doc_number] => 04891331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-01-02 [patent_title] => 'Method for doping silicon wafers using Al.sub.2 O.sub.3 /P.sub.2 O.sub.5 composition' [patent_app_type] => 1 [patent_app_number] => 7/146503 [patent_app_country] => US [patent_app_date] => 1988-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2202 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/891/04891331.pdf [firstpage_image] =>[orig_patent_app_number] => 146503 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/146503
Method for doping silicon wafers using Al.sub.2 O.sub.3 /P.sub.2 O.sub.5 composition Jan 20, 1988 Issued
Array ( [id] => 2551162 [patent_doc_number] => 04833096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-23 [patent_title] => 'EEPROM fabrication process' [patent_app_type] => 1 [patent_app_number] => 7/145467 [patent_app_country] => US [patent_app_date] => 1988-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 4862 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/833/04833096.pdf [firstpage_image] =>[orig_patent_app_number] => 145467 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/145467
EEPROM fabrication process Jan 18, 1988 Issued
Array ( [id] => 2515790 [patent_doc_number] => 04874711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-10-17 [patent_title] => 'Method for altering characteristics of active semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/145623 [patent_app_country] => US [patent_app_date] => 1988-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3906 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/874/04874711.pdf [firstpage_image] =>[orig_patent_app_number] => 145623 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/145623
Method for altering characteristics of active semiconductor devices Jan 18, 1988 Issued
Array ( [id] => 2656315 [patent_doc_number] => 04971925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-20 [patent_title] => 'Improved method of manufacturing a semiconductor device of the \"semiconductor on insulator\" type' [patent_app_type] => 1 [patent_app_number] => 7/142763 [patent_app_country] => US [patent_app_date] => 1988-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 1885 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/971/04971925.pdf [firstpage_image] =>[orig_patent_app_number] => 142763 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/142763
Improved method of manufacturing a semiconductor device of the "semiconductor on insulator" type Jan 10, 1988 Issued
Menu