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Olik Chaudhuri

Supervisory Patent Examiner (ID: 4041, Phone: (571)272-9820 , Office: P/2823 )

Most Active Art Unit
1104
Art Unit(s)
1104, 2823, 2814, 1106, 1107
Total Applications
949
Issued Applications
761
Pending Applications
4
Abandoned Applications
184

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2508186 [patent_doc_number] => 04830974 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-16 [patent_title] => 'EPROM fabrication process' [patent_app_type] => 1 [patent_app_number] => 7/142641 [patent_app_country] => US [patent_app_date] => 1988-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 4803 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/830/04830974.pdf [firstpage_image] =>[orig_patent_app_number] => 142641 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/142641
EPROM fabrication process Jan 10, 1988 Issued
Array ( [id] => 2508760 [patent_doc_number] => 04818369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-04 [patent_title] => 'Liquid effluent recycle to reactor in dewaxing processes' [patent_app_type] => 1 [patent_app_number] => 7/140873 [patent_app_country] => US [patent_app_date] => 1988-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2435 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/818/04818369.pdf [firstpage_image] =>[orig_patent_app_number] => 140873 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/140873
Liquid effluent recycle to reactor in dewaxing processes Jan 5, 1988 Issued
Array ( [id] => 2709822 [patent_doc_number] => 05009869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-23 [patent_title] => 'Methods for purification of air' [patent_app_type] => 1 [patent_app_number] => 7/138441 [patent_app_country] => US [patent_app_date] => 1987-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6743 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/009/05009869.pdf [firstpage_image] =>[orig_patent_app_number] => 138441 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/138441
Methods for purification of air Dec 27, 1987 Issued
Array ( [id] => 2475634 [patent_doc_number] => 04865656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-12 [patent_title] => 'Process for surface passivation of an indium phosphide substrate and product obtained' [patent_app_type] => 1 [patent_app_number] => 7/133046 [patent_app_country] => US [patent_app_date] => 1987-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2048 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/865/04865656.pdf [firstpage_image] =>[orig_patent_app_number] => 133046 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/133046
Process for surface passivation of an indium phosphide substrate and product obtained Dec 27, 1987 Issued
07/131739 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE Dec 10, 1987 Abandoned
Array ( [id] => 2475617 [patent_doc_number] => 04889817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-26 [patent_title] => 'Method of manufacturing schottky gate field transistor by ion implantation method' [patent_app_type] => 1 [patent_app_number] => 7/132713 [patent_app_country] => US [patent_app_date] => 1987-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3892 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/889/04889817.pdf [firstpage_image] =>[orig_patent_app_number] => 132713 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/132713
Method of manufacturing schottky gate field transistor by ion implantation method Dec 10, 1987 Issued
Array ( [id] => 2523716 [patent_doc_number] => 04883775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-11-28 [patent_title] => 'Process for cleaning and protecting semiconductor substrates' [patent_app_type] => 1 [patent_app_number] => 7/131072 [patent_app_country] => US [patent_app_date] => 1987-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4723 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/883/04883775.pdf [firstpage_image] =>[orig_patent_app_number] => 131072 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/131072
Process for cleaning and protecting semiconductor substrates Dec 9, 1987 Issued
Array ( [id] => 2484227 [patent_doc_number] => 04820654 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-11 [patent_title] => 'Isolation of regions in a CMOS structure using selective epitaxial growth' [patent_app_type] => 1 [patent_app_number] => 7/130481 [patent_app_country] => US [patent_app_date] => 1987-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2428 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/820/04820654.pdf [firstpage_image] =>[orig_patent_app_number] => 130481 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/130481
Isolation of regions in a CMOS structure using selective epitaxial growth Dec 8, 1987 Issued
Array ( [id] => 2560642 [patent_doc_number] => 04835115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-30 [patent_title] => 'Method for forming oxide-capped trench isolation' [patent_app_type] => 1 [patent_app_number] => 7/129270 [patent_app_country] => US [patent_app_date] => 1987-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4168 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/835/04835115.pdf [firstpage_image] =>[orig_patent_app_number] => 129270 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/129270
Method for forming oxide-capped trench isolation Dec 6, 1987 Issued
07/127428 METHOD OF FORMING REFRACTORY METAL FILM Dec 1, 1987 Abandoned
Array ( [id] => 2488374 [patent_doc_number] => 04859614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-22 [patent_title] => 'Method for manufacturing semiconductor device with leads adhered to supporting insulator sheet' [patent_app_type] => 1 [patent_app_number] => 7/126514 [patent_app_country] => US [patent_app_date] => 1987-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 1966 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/859/04859614.pdf [firstpage_image] =>[orig_patent_app_number] => 126514 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/126514
Method for manufacturing semiconductor device with leads adhered to supporting insulator sheet Nov 29, 1987 Issued
Array ( [id] => 2625626 [patent_doc_number] => 04920070 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-04-24 [patent_title] => 'Method for forming wirings for a semiconductor device by filling very narrow via holes' [patent_app_type] => 1 [patent_app_number] => 7/127042 [patent_app_country] => US [patent_app_date] => 1987-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 30 [patent_no_of_words] => 6264 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/920/04920070.pdf [firstpage_image] =>[orig_patent_app_number] => 127042 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/127042
Method for forming wirings for a semiconductor device by filling very narrow via holes Nov 26, 1987 Issued
Array ( [id] => 2474698 [patent_doc_number] => 04812418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-14 [patent_title] => 'Micron and submicron patterning without using a lithographic mask having submicron dimensions' [patent_app_type] => 1 [patent_app_number] => 7/125972 [patent_app_country] => US [patent_app_date] => 1987-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2220 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/812/04812418.pdf [firstpage_image] =>[orig_patent_app_number] => 125972 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/125972
Micron and submicron patterning without using a lithographic mask having submicron dimensions Nov 26, 1987 Issued
Array ( [id] => 2560561 [patent_doc_number] => 04835111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-30 [patent_title] => 'Method of fabricating self-aligned zener diode' [patent_app_type] => 1 [patent_app_number] => 7/125015 [patent_app_country] => US [patent_app_date] => 1987-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2299 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/835/04835111.pdf [firstpage_image] =>[orig_patent_app_number] => 125015 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/125015
Method of fabricating self-aligned zener diode Nov 23, 1987 Issued
Array ( [id] => 2635988 [patent_doc_number] => 04910158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-03-20 [patent_title] => 'Zener diode emulation and method of forming the same' [patent_app_type] => 1 [patent_app_number] => 7/124231 [patent_app_country] => US [patent_app_date] => 1987-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2193 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/910/04910158.pdf [firstpage_image] =>[orig_patent_app_number] => 124231 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/124231
Zener diode emulation and method of forming the same Nov 22, 1987 Issued
Array ( [id] => 2560599 [patent_doc_number] => 04835113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-30 [patent_title] => 'Fabrication of dielectrically isolated devices with buried conductive layers' [patent_app_type] => 1 [patent_app_number] => 7/123695 [patent_app_country] => US [patent_app_date] => 1987-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/835/04835113.pdf [firstpage_image] =>[orig_patent_app_number] => 123695 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/123695
Fabrication of dielectrically isolated devices with buried conductive layers Nov 22, 1987 Issued
07/123757 CONSTANT WIDTH TRENCH FOR WAFER PROCESSING Nov 22, 1987 Abandoned
Array ( [id] => 2445880 [patent_doc_number] => 04791073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-13 [patent_title] => 'Trench isolation method for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 7/122094 [patent_app_country] => US [patent_app_date] => 1987-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 4614 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/791/04791073.pdf [firstpage_image] =>[orig_patent_app_number] => 122094 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/122094
Trench isolation method for semiconductor devices Nov 16, 1987 Issued
07/122091 MULTILAYER TRENCH ISOLATION PROCESS AND STRUCTURE Nov 16, 1987 Abandoned
Array ( [id] => 2641077 [patent_doc_number] => 04939104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-03 [patent_title] => 'Method for forming a buried lateral contact' [patent_app_type] => 1 [patent_app_number] => 7/122604 [patent_app_country] => US [patent_app_date] => 1987-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 3687 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/939/04939104.pdf [firstpage_image] =>[orig_patent_app_number] => 122604 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/122604
Method for forming a buried lateral contact Nov 16, 1987 Issued
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