Olik Chaudhuri

Array ( [id] => 2413339 [patent_doc_number] => 04742016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-03 [patent_title] => 'Method of manufacture of a two-phase CCD' [patent_app_type] => 1 [patent_app_number] => 7/031975 [patent_app_country] => US [patent_app_date] => 1987-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2631 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/742/04742016.pdf [firstpage_image] =>[orig_patent_app_number] => 031975 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2385110 [patent_doc_number] => 04789642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-06 [patent_title] => 'Method for fabricating low loss crystalline silicon waveguides by dielectric implantation' [patent_app_type] => 1 [patent_app_number] => 7/032810 [patent_app_country] => US [patent_app_date] => 1987-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 3290 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/789/04789642.pdf [firstpage_image] =>[orig_patent_app_number] => 032810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2446607 [patent_doc_number] => 04755477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-07-05 [patent_title] => 'Overhang isolation technology' [patent_app_type] => 1 [patent_app_number] => 7/029621 [patent_app_country] => US [patent_app_date] => 1987-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3205 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/755/04755477.pdf [firstpage_image] =>[orig_patent_app_number] => 029621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2508270 [patent_doc_number] => 04830978 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-16 [patent_title] => 'Dram cell and method' [patent_app_type] => 1 [patent_app_number] => 7/026356 [patent_app_country] => US [patent_app_date] => 1987-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 39 [patent_no_of_words] => 5099 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/830/04830978.pdf [firstpage_image] =>[orig_patent_app_number] => 026356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2415915 [patent_doc_number] => 04728622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-03-01 [patent_title] => 'Charge transfer device having a width changing channel' [patent_app_type] => 1 [patent_app_number] => 7/042091 [patent_app_country] => US [patent_app_date] => 1987-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2269 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/728/04728622.pdf [firstpage_image] =>[orig_patent_app_number] => 042091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2414085 [patent_doc_number] => 04719184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-01-12 [patent_title] => 'Process for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistors' [patent_app_type] => 1 [patent_app_number] => 7/022482 [patent_app_country] => US [patent_app_date] => 1987-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 1299 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/719/04719184.pdf [firstpage_image] =>[orig_patent_app_number] => 022482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2516554 [patent_doc_number] => 04870033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-09-26 [patent_title] => 'Method of manufacturing a multilayer electrode containing silicide for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/021187 [patent_app_country] => US [patent_app_date] => 1987-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3678 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/870/04870033.pdf [firstpage_image] =>[orig_patent_app_number] => 021187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2444629 [patent_doc_number] => 04740483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-04-26 [patent_title] => 'Selective LPCVD tungsten deposition by nitridation of a dielectric' [patent_app_type] => 1 [patent_app_number] => 7/020847 [patent_app_country] => US [patent_app_date] => 1987-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2848 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/740/04740483.pdf [firstpage_image] =>[orig_patent_app_number] => 020847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2550971 [patent_doc_number] => 04814285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-21 [patent_title] => 'Method for forming planarized interconnect level using selective deposition and ion implantation' [patent_app_type] => 1 [patent_app_number] => 7/019697 [patent_app_country] => US [patent_app_date] => 1987-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2195 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/814/04814285.pdf [firstpage_image] =>[orig_patent_app_number] => 019697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2422875 [patent_doc_number] => 04774198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-09-27 [patent_title] => 'Self-aligned process for fabricating small DMOS cells' [patent_app_type] => 1 [patent_app_number] => 7/019785 [patent_app_country] => US [patent_app_date] => 1987-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2899 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/774/04774198.pdf [firstpage_image] =>[orig_patent_app_number] => 019785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2508232 [patent_doc_number] => 04830976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-16 [patent_title] => 'Integrated circuit resistor' [patent_app_type] => 1 [patent_app_number] => 7/016455 [patent_app_country] => US [patent_app_date] => 1987-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5241 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/830/04830976.pdf [firstpage_image] =>[orig_patent_app_number] => 016455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2415807 [patent_doc_number] => 04728616 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-03-01 [patent_title] => 'Ballistic heterojunction bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 7/016893 [patent_app_country] => US [patent_app_date] => 1987-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 3100 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/728/04728616.pdf [firstpage_image] =>[orig_patent_app_number] => 016893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2479348 [patent_doc_number] => 04820404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-04-11 [patent_title] => 'Cooling of stripped catalyst prior to regeneration in cracking process' [patent_app_type] => 1 [patent_app_number] => 7/014964 [patent_app_country] => US [patent_app_date] => 1987-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5810 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/820/04820404.pdf [firstpage_image] =>[orig_patent_app_number] => 014964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2415552 [patent_doc_number] => 04746625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-24 [patent_title] => 'A method of manufacturing semiconductor elements-isolating silicon oxide layers' [patent_app_type] => 1 [patent_app_number] => 7/015037 [patent_app_country] => US [patent_app_date] => 1987-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2377 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/746/04746625.pdf [firstpage_image] =>[orig_patent_app_number] => 015037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2393260 [patent_doc_number] => 04769339 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-09-06 [patent_title] => 'Method of manufacturing a field effect transistor device having a multilayer gate electrode' [patent_app_type] => 1 [patent_app_number] => 7/013794 [patent_app_country] => US [patent_app_date] => 1987-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 3068 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/769/04769339.pdf [firstpage_image] =>[orig_patent_app_number] => 013794 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2411302 [patent_doc_number] => 04761385 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-08-02 [patent_title] => 'Forming a trench capacitor' [patent_app_type] => 1 [patent_app_number] => 7/013096 [patent_app_country] => US [patent_app_date] => 1987-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2359 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/761/04761385.pdf [firstpage_image] =>[orig_patent_app_number] => 013096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2418388 [patent_doc_number] => 04748131 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-31 [patent_title] => 'Method for increasing radiation hardness of MOS gate oxides' [patent_app_type] => 1 [patent_app_number] => 7/011563 [patent_app_country] => US [patent_app_date] => 1987-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1856 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/748/04748131.pdf [firstpage_image] =>[orig_patent_app_number] => 011563 [rel_patent_id] =>[rel_patent_doc_number] =>)