Olivia T. Luk

Array ( [id] => 4309605 [patent_doc_number] => 06316277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Tuning substrate/resist contrast to maximize defect inspection sensitivity for ultra-thin resist in DUV lithography' [patent_app_type] => 1 [patent_app_number] => 9/580612 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 3169 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316277.pdf [firstpage_image] =>[orig_patent_app_number] => 580612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4358618 [patent_doc_number] => 06255196 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions' [patent_app_type] => 1 [patent_app_number] => 9/567262 [patent_app_country] => US [patent_app_date] => 2000-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255196.pdf [firstpage_image] =>[orig_patent_app_number] => 567262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459636 [patent_doc_number] => 06391796 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method for heat-treating silicon wafer and silicon wafer' [patent_app_type] => B1 [patent_app_number] => 09/530602 [patent_app_country] => US [patent_app_date] => 2000-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5759 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391796.pdf [firstpage_image] =>[orig_patent_app_number] => 09530602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4327354 [patent_doc_number] => 06319820 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Fabrication method for dual damascene structure' [patent_app_type] => 1 [patent_app_number] => 9/561578 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 3871 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319820.pdf [firstpage_image] =>[orig_patent_app_number] => 561578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4408300 [patent_doc_number] => 06309943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Precision marking and singulation method' [patent_app_type] => 1 [patent_app_number] => 9/558392 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7696 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309943.pdf [firstpage_image] =>[orig_patent_app_number] => 558392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1336640 [patent_doc_number] => 06593247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method of depositing low k films using an oxidizing plasma' [patent_app_type] => B1 [patent_app_number] => 09/553461 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 8960 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593247.pdf [firstpage_image] =>[orig_patent_app_number] => 09553461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1446511 [patent_doc_number] => 06368884 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Die-based in-fab process monitoring and analysis system for semiconductor processing' [patent_app_type] => B1 [patent_app_number] => 09/548142 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 12189 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368884.pdf [firstpage_image] =>[orig_patent_app_number] => 09548142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4380369 [patent_doc_number] => 06261853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Method and apparatus for preparing semiconductor wafers for measurement' [patent_app_type] => 1 [patent_app_number] => 9/499478 [patent_app_country] => US [patent_app_date] => 2000-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3831 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/261/06261853.pdf [firstpage_image] =>[orig_patent_app_number] => 499478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4250303 [patent_doc_number] => 06207542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method for establishing ultra-thin gate insulator using oxidized nitride film' [patent_app_type] => 1 [patent_app_number] => 9/478962 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1621 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207542.pdf [firstpage_image] =>[orig_patent_app_number] => 478962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302333 [patent_doc_number] => 06251762 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method and device for improved salicide resistance on polysilicon gates' [patent_app_type] => 1 [patent_app_number] => 9/458572 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 57 [patent_no_of_words] => 6188 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251762.pdf [firstpage_image] =>[orig_patent_app_number] => 458572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1433314 [patent_doc_number] => 06340604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Contactor and semiconductor device inspecting method' [patent_app_type] => B1 [patent_app_number] => 09/455151 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5477 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340604.pdf [firstpage_image] =>[orig_patent_app_number] => 09455151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1528105 [patent_doc_number] => 06479370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Isolated structure and method of fabricating such a structure on a substrate' [patent_app_type] => B2 [patent_app_number] => 09/440406 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3831 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479370.pdf [firstpage_image] =>[orig_patent_app_number] => 09440406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1528105 [patent_doc_number] => 06479370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Isolated structure and method of fabricating such a structure on a substrate' [patent_app_type] => B2 [patent_app_number] => 09/440406 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3831 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479370.pdf [firstpage_image] =>[orig_patent_app_number] => 09440406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1528105 [patent_doc_number] => 06479370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Isolated structure and method of fabricating such a structure on a substrate' [patent_app_type] => B2 [patent_app_number] => 09/440406 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3831 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479370.pdf [firstpage_image] =>[orig_patent_app_number] => 09440406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1528105 [patent_doc_number] => 06479370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Isolated structure and method of fabricating such a structure on a substrate' [patent_app_type] => B2 [patent_app_number] => 09/440406 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3831 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479370.pdf [firstpage_image] =>[orig_patent_app_number] => 09440406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4357255 [patent_doc_number] => 06190977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method for forming MOSFET with an elevated source/drain' [patent_app_type] => 1 [patent_app_number] => 9/439431 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3391 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190977.pdf [firstpage_image] =>[orig_patent_app_number] => 439431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1494126 [patent_doc_number] => 06342399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Testing integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/435971 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2697 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342399.pdf [firstpage_image] =>[orig_patent_app_number] => 09435971 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4318228 [patent_doc_number] => 06248602 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method and apparatus for automated rework within run-to-run control semiconductor manufacturing' [patent_app_type] => 1 [patent_app_number] => 9/430862 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6723 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248602.pdf [firstpage_image] =>[orig_patent_app_number] => 430862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4420130 [patent_doc_number] => 06225170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Self-aligned damascene gate with contact formation' [patent_app_type] => 1 [patent_app_number] => 9/428481 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2628 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225170.pdf [firstpage_image] =>[orig_patent_app_number] => 428481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4258049 [patent_doc_number] => 06258611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for determining translation portion of misalignment error in a stepper' [patent_app_type] => 1 [patent_app_number] => 9/422912 [patent_app_country] => US [patent_app_date] => 1999-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 11 [patent_no_of_words] => 6255 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/258/06258611.pdf [firstpage_image] =>[orig_patent_app_number] => 422912 [rel_patent_id] =>[rel_patent_doc_number] =>)