Search

Olivia T. Luk

Examiner (ID: 10459)

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
278
Issued Applications
256
Pending Applications
8
Abandoned Applications
14

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1458804 [patent_doc_number] => 06426269 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Dummy feature reduction using optical proximity effect correction' [patent_app_type] => B1 [patent_app_number] => 09/422634 [patent_app_country] => US [patent_app_date] => 1999-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3934 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426269.pdf [firstpage_image] =>[orig_patent_app_number] => 09422634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422634
Dummy feature reduction using optical proximity effect correction Oct 20, 1999 Issued
Array ( [id] => 1449841 [patent_doc_number] => 06455334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Probe grid for integrated circuit analysis' [patent_app_type] => B1 [patent_app_number] => 09/409982 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2807 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455334.pdf [firstpage_image] =>[orig_patent_app_number] => 09409982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409982
Probe grid for integrated circuit analysis Sep 29, 1999 Issued
Array ( [id] => 4286534 [patent_doc_number] => 06268241 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method of forming a self-aligned silicide structure in integrated circuit fabrication' [patent_app_type] => 1 [patent_app_number] => 9/408152 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1737 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268241.pdf [firstpage_image] =>[orig_patent_app_number] => 408152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408152
Method of forming a self-aligned silicide structure in integrated circuit fabrication Sep 28, 1999 Issued
Array ( [id] => 4407679 [patent_doc_number] => 06300145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Ion implantation and laser anneal to create n-doped structures in silicon' [patent_app_type] => 1 [patent_app_number] => 9/408051 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1902 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300145.pdf [firstpage_image] =>[orig_patent_app_number] => 408051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408051
Ion implantation and laser anneal to create n-doped structures in silicon Sep 28, 1999 Issued
Array ( [id] => 4380517 [patent_doc_number] => 06277659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Substrate removal using thermal analysis' [patent_app_type] => 1 [patent_app_number] => 9/409011 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277659.pdf [firstpage_image] =>[orig_patent_app_number] => 409011 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409011
Substrate removal using thermal analysis Sep 28, 1999 Issued
Array ( [id] => 4311912 [patent_doc_number] => 06242273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Fractal filter applied to a contamination-free manufacturing signal to improve signal-to-noise ratios' [patent_app_type] => 1 [patent_app_number] => 9/408232 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 7603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242273.pdf [firstpage_image] =>[orig_patent_app_number] => 408232 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408232
Fractal filter applied to a contamination-free manufacturing signal to improve signal-to-noise ratios Sep 28, 1999 Issued
Array ( [id] => 1602550 [patent_doc_number] => 06432729 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method for characterization of microelectronic feature quality' [patent_app_type] => B1 [patent_app_number] => 09/408419 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8620 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432729.pdf [firstpage_image] =>[orig_patent_app_number] => 09408419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408419
Method for characterization of microelectronic feature quality Sep 28, 1999 Issued
Array ( [id] => 4376869 [patent_doc_number] => 06303396 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Substrate removal as a function of resistance at the back side of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/408881 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303396.pdf [firstpage_image] =>[orig_patent_app_number] => 408881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408881
Substrate removal as a function of resistance at the back side of a semiconductor device Sep 28, 1999 Issued
Array ( [id] => 1527971 [patent_doc_number] => 06479305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => B2 [patent_app_number] => 09/396732 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 8462 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479305.pdf [firstpage_image] =>[orig_patent_app_number] => 09396732 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396732
Semiconductor device manufacturing method Sep 14, 1999 Issued
Array ( [id] => 1459175 [patent_doc_number] => 06391663 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Methods of sensing temperature of an electronic device workpiece and methods of semiconductor processing' [patent_app_type] => B1 [patent_app_number] => 09/389924 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3931 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391663.pdf [firstpage_image] =>[orig_patent_app_number] => 09389924 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389924
Methods of sensing temperature of an electronic device workpiece and methods of semiconductor processing Sep 2, 1999 Abandoned
Array ( [id] => 1585701 [patent_doc_number] => 06358862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Passivation integrity improvements' [patent_app_type] => B1 [patent_app_number] => 09/389658 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2110 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358862.pdf [firstpage_image] =>[orig_patent_app_number] => 09389658 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389658
Passivation integrity improvements Sep 1, 1999 Issued
Array ( [id] => 4380711 [patent_doc_number] => 06294395 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Back side reactive ion etch' [patent_app_type] => 1 [patent_app_number] => 9/383791 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2373 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294395.pdf [firstpage_image] =>[orig_patent_app_number] => 383791 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383791
Back side reactive ion etch Aug 25, 1999 Issued
Array ( [id] => 4266186 [patent_doc_number] => 06306670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Tool for handling a workpiece' [patent_app_type] => 1 [patent_app_number] => 9/373354 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1653 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306670.pdf [firstpage_image] =>[orig_patent_app_number] => 373354 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/373354
Tool for handling a workpiece Aug 11, 1999 Issued
Array ( [id] => 4350777 [patent_doc_number] => 06291329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Protective oxide buffer layer for ARC removal' [patent_app_type] => 1 [patent_app_number] => 9/371921 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1873 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291329.pdf [firstpage_image] =>[orig_patent_app_number] => 371921 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371921
Protective oxide buffer layer for ARC removal Aug 10, 1999 Issued
Array ( [id] => 1435903 [patent_doc_number] => 06355546 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Thermally grown protective oxide buffer layer for ARC removal' [patent_app_type] => B1 [patent_app_number] => 09/371922 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1697 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/355/06355546.pdf [firstpage_image] =>[orig_patent_app_number] => 09371922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371922
Thermally grown protective oxide buffer layer for ARC removal Aug 10, 1999 Issued
Array ( [id] => 1600456 [patent_doc_number] => 06475895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Semiconductor device having a passivation layer and method for its fabrication' [patent_app_type] => B1 [patent_app_number] => 09/369982 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2268 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475895.pdf [firstpage_image] =>[orig_patent_app_number] => 09369982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/369982
Semiconductor device having a passivation layer and method for its fabrication Aug 5, 1999 Issued
Array ( [id] => 1370865 [patent_doc_number] => 06562636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Wafer level burn-in and electrical test system and method' [patent_app_type] => B1 [patent_app_number] => 09/353121 [patent_app_country] => US [patent_app_date] => 1999-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 5166 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562636.pdf [firstpage_image] =>[orig_patent_app_number] => 09353121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/353121
Wafer level burn-in and electrical test system and method Jul 13, 1999 Issued
Array ( [id] => 4269196 [patent_doc_number] => 06245584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method for detecting adjustment error in photolithographic stepping printer' [patent_app_type] => 1 [patent_app_number] => 9/346632 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2608 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245584.pdf [firstpage_image] =>[orig_patent_app_number] => 346632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346632
Method for detecting adjustment error in photolithographic stepping printer Jun 30, 1999 Issued
Array ( [id] => 4405526 [patent_doc_number] => 06171887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Semiconductor device for a face down bonding to a mounting substrate and a method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/304633 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3086 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171887.pdf [firstpage_image] =>[orig_patent_app_number] => 304633 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304633
Semiconductor device for a face down bonding to a mounting substrate and a method of manufacturing the same May 3, 1999 Issued
Array ( [id] => 4327951 [patent_doc_number] => 06213347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Low stress method and apparatus of underfilling flip-chip electronic devices' [patent_app_type] => 1 [patent_app_number] => 9/305332 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6387 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/213/06213347.pdf [firstpage_image] =>[orig_patent_app_number] => 305332 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/305332
Low stress method and apparatus of underfilling flip-chip electronic devices Apr 29, 1999 Issued
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