Search

Olivia T. Luk

Examiner (ID: 10459)

Most Active Art Unit
2812
Art Unit(s)
2812
Total Applications
278
Issued Applications
256
Pending Applications
8
Abandoned Applications
14

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1453382 [patent_doc_number] => 06461880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method for monitoring silicide failures' [patent_app_type] => B1 [patent_app_number] => 09/892752 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2280 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461880.pdf [firstpage_image] =>[orig_patent_app_number] => 09892752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892752
Method for monitoring silicide failures Jun 27, 2001 Issued
Array ( [id] => 7645734 [patent_doc_number] => 06472235 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Apparatus and method for preparing backside-ground wafers for testing' [patent_app_type] => B1 [patent_app_number] => 09/886881 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3392 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472235.pdf [firstpage_image] =>[orig_patent_app_number] => 09886881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886881
Apparatus and method for preparing backside-ground wafers for testing Jun 20, 2001 Issued
Array ( [id] => 1397947 [patent_doc_number] => 06537833 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method and apparatus for characterizing an interconnect structure profile using scatterometry measurements' [patent_app_type] => B1 [patent_app_number] => 09/885411 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3891 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537833.pdf [firstpage_image] =>[orig_patent_app_number] => 09885411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/885411
Method and apparatus for characterizing an interconnect structure profile using scatterometry measurements Jun 18, 2001 Issued
Array ( [id] => 1458945 [patent_doc_number] => 06426307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method of manufacturing an aluminum oxide film in a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/882011 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1615 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426307.pdf [firstpage_image] =>[orig_patent_app_number] => 09882011 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882011
Method of manufacturing an aluminum oxide film in a semiconductor device Jun 14, 2001 Issued
Array ( [id] => 1290929 [patent_doc_number] => 06630362 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method and apparatus for performing trench depth analysis' [patent_app_type] => B1 [patent_app_number] => 09/880990 [patent_app_country] => US [patent_app_date] => 2001-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5611 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/630/06630362.pdf [firstpage_image] =>[orig_patent_app_number] => 09880990 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880990
Method and apparatus for performing trench depth analysis Jun 12, 2001 Issued
Array ( [id] => 1361083 [patent_doc_number] => 06569693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-27 [patent_title] => 'Method for fabricating epitaxial substrate' [patent_app_type] => B2 [patent_app_number] => 09/865482 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4656 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569693.pdf [firstpage_image] =>[orig_patent_app_number] => 09865482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865482
Method for fabricating epitaxial substrate May 28, 2001 Issued
Array ( [id] => 5873982 [patent_doc_number] => 20020048826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Wafer level burn-in and electrical test system and method' [patent_app_type] => new [patent_app_number] => 09/865957 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5216 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048826.pdf [firstpage_image] =>[orig_patent_app_number] => 09865957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865957
Wafer level burn-in and electrical test system and method May 24, 2001 Issued
Array ( [id] => 6901530 [patent_doc_number] => 20010023113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Method for sawing wafers employing multiple indexing techniques for multiple die dimensions' [patent_app_type] => new [patent_app_number] => 09/864911 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20010023113.pdf [firstpage_image] =>[orig_patent_app_number] => 09864911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864911
Method for sawing wafers employing multiple indexing techniques for multiple die dimensions May 22, 2001 Issued
Array ( [id] => 1532300 [patent_doc_number] => 06410352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-25 [patent_title] => 'Apparatus and method for testing fuses' [patent_app_type] => B2 [patent_app_number] => 09/854541 [patent_app_country] => US [patent_app_date] => 2001-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5655 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410352.pdf [firstpage_image] =>[orig_patent_app_number] => 09854541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/854541
Apparatus and method for testing fuses May 13, 2001 Issued
Array ( [id] => 1318494 [patent_doc_number] => 06611308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Cone protrusion in multi-domain vertically aligned liquid crystal display' [patent_app_type] => B2 [patent_app_number] => 09/845520 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1555 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611308.pdf [firstpage_image] =>[orig_patent_app_number] => 09845520 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845520
Cone protrusion in multi-domain vertically aligned liquid crystal display Apr 29, 2001 Issued
Array ( [id] => 1382851 [patent_doc_number] => 06551949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Deposition method of dielectric films having a low dielectric constant' [patent_app_type] => B2 [patent_app_number] => 09/845052 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1851 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551949.pdf [firstpage_image] =>[orig_patent_app_number] => 09845052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845052
Deposition method of dielectric films having a low dielectric constant Apr 26, 2001 Issued
Array ( [id] => 1594170 [patent_doc_number] => 06383824 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of using scatterometry measurements to control deposition processes' [patent_app_type] => B1 [patent_app_number] => 09/843111 [patent_app_country] => US [patent_app_date] => 2001-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5172 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383824.pdf [firstpage_image] =>[orig_patent_app_number] => 09843111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/843111
Method of using scatterometry measurements to control deposition processes Apr 24, 2001 Issued
Array ( [id] => 6464447 [patent_doc_number] => 20020021392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Liquid crystal display element and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/840126 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5346 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20020021392.pdf [firstpage_image] =>[orig_patent_app_number] => 09840126 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/840126
Liquid crystal display element and method of manufacturing the same Apr 23, 2001 Issued
Array ( [id] => 6175483 [patent_doc_number] => 20020155387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'METHOD AND APPARATUS FOR IMPROVING RESOLUTION OF OBJECTS IN A SEMICONDUCTOR WAFER' [patent_app_type] => new [patent_app_number] => 09/841762 [patent_app_country] => US [patent_app_date] => 2001-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1853 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20020155387.pdf [firstpage_image] =>[orig_patent_app_number] => 09841762 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841762
Method and apparatus for improving resolution of objects in a semiconductor wafer Apr 23, 2001 Issued
Array ( [id] => 1559589 [patent_doc_number] => 06436728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method for making an optical waveguide substrate' [patent_app_type] => B2 [patent_app_number] => 09/836272 [patent_app_country] => US [patent_app_date] => 2001-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2816 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436728.pdf [firstpage_image] =>[orig_patent_app_number] => 09836272 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/836272
Method for making an optical waveguide substrate Apr 17, 2001 Issued
Array ( [id] => 6921619 [patent_doc_number] => 20010029104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Substrate-cleaning method and substrate-cleaning solution' [patent_app_type] => new [patent_app_number] => 09/835412 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8835 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20010029104.pdf [firstpage_image] =>[orig_patent_app_number] => 09835412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/835412
Substrate-cleaning method and substrate-cleaning solution Apr 16, 2001 Issued
Array ( [id] => 7078614 [patent_doc_number] => 20010041460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Method of depositing dielectric' [patent_app_type] => new [patent_app_number] => 09/832942 [patent_app_country] => US [patent_app_date] => 2001-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1148 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20010041460.pdf [firstpage_image] =>[orig_patent_app_number] => 09832942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832942
Method of depositing dielectric Apr 11, 2001 Abandoned
Array ( [id] => 1581103 [patent_doc_number] => 06423602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-23 [patent_title] => 'Circuit manufacturing method and apparatus, anneal control method and apparatus, information storage medium' [patent_app_type] => B2 [patent_app_number] => 09/834032 [patent_app_country] => US [patent_app_date] => 2001-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 5740 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423602.pdf [firstpage_image] =>[orig_patent_app_number] => 09834032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/834032
Circuit manufacturing method and apparatus, anneal control method and apparatus, information storage medium Apr 11, 2001 Issued
Array ( [id] => 1181114 [patent_doc_number] => 06737361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-18 [patent_title] => 'Method for H2 Recycling in semiconductor processing system' [patent_app_type] => B2 [patent_app_number] => 09/828518 [patent_app_country] => US [patent_app_date] => 2001-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2634 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/737/06737361.pdf [firstpage_image] =>[orig_patent_app_number] => 09828518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/828518
Method for H2 Recycling in semiconductor processing system Apr 5, 2001 Issued
Array ( [id] => 1514599 [patent_doc_number] => 06420280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-16 [patent_title] => 'Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer' [patent_app_type] => B2 [patent_app_number] => 09/825672 [patent_app_country] => US [patent_app_date] => 2001-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4228 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420280.pdf [firstpage_image] =>[orig_patent_app_number] => 09825672 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/825672
Method and system for reducing ARC layer removal by providing a capping layer for the ARC layer Apr 2, 2001 Issued
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