Search

Olvin Lopez Alvarez

Examiner (ID: 16078)

Most Active Art Unit
2117
Art Unit(s)
2121, 2117, 4123, 2125
Total Applications
566
Issued Applications
261
Pending Applications
47
Abandoned Applications
274

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3767388 [patent_doc_number] => 05721874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Configurable cache with variable, dynamically addressable line sizes' [patent_app_type] => 1 [patent_app_number] => 8/491375 [patent_app_country] => US [patent_app_date] => 1995-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2467 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721874.pdf [firstpage_image] =>[orig_patent_app_number] => 491375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/491375
Configurable cache with variable, dynamically addressable line sizes Jun 15, 1995 Issued
Array ( [id] => 3562286 [patent_doc_number] => 05548738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'System and method for processing an instruction in a processing system' [patent_app_type] => 1 [patent_app_number] => 8/483905 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 38 [patent_no_of_words] => 13119 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548738.pdf [firstpage_image] =>[orig_patent_app_number] => 483905 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/483905
System and method for processing an instruction in a processing system Jun 6, 1995 Issued
Array ( [id] => 3622374 [patent_doc_number] => 05590377 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Automatic control of distributed DMAs in a PCI bus system supporting dual ISA buses' [patent_app_type] => 1 [patent_app_number] => 8/481121 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6007 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/590/05590377.pdf [firstpage_image] =>[orig_patent_app_number] => 481121 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/481121
Automatic control of distributed DMAs in a PCI bus system supporting dual ISA buses Jun 6, 1995 Issued
Array ( [id] => 3745387 [patent_doc_number] => 05694577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Memory conflict buffer for achieving memory disambiguation in compile-time code schedule' [patent_app_type] => 1 [patent_app_number] => 8/470825 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6334 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694577.pdf [firstpage_image] =>[orig_patent_app_number] => 470825 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/470825
Memory conflict buffer for achieving memory disambiguation in compile-time code schedule Jun 5, 1995 Issued
Array ( [id] => 3603706 [patent_doc_number] => 05586295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Combination prefetch buffer and instruction cache' [patent_app_type] => 1 [patent_app_number] => 8/462009 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5627 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/586/05586295.pdf [firstpage_image] =>[orig_patent_app_number] => 462009 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/462009
Combination prefetch buffer and instruction cache Jun 4, 1995 Issued
Array ( [id] => 3673063 [patent_doc_number] => 05649143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Apparatus and method for providing a cache indexing scheme less susceptible to cache collisions' [patent_app_type] => 1 [patent_app_number] => 8/459755 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3803 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649143.pdf [firstpage_image] =>[orig_patent_app_number] => 459755 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/459755
Apparatus and method for providing a cache indexing scheme less susceptible to cache collisions Jun 1, 1995 Issued
Array ( [id] => 3738425 [patent_doc_number] => 05652858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Method for prefetching pointer-type data structure and information processing apparatus therefor' [patent_app_type] => 1 [patent_app_number] => 8/455335 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 8696 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652858.pdf [firstpage_image] =>[orig_patent_app_number] => 455335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/455335
Method for prefetching pointer-type data structure and information processing apparatus therefor May 30, 1995 Issued
Array ( [id] => 3669963 [patent_doc_number] => 05659712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Pipelined microprocessor that prevents the cache from being read when the contents of the cache are invalid' [patent_app_type] => 1 [patent_app_number] => 8/452659 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2562 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659712.pdf [firstpage_image] =>[orig_patent_app_number] => 452659 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/452659
Pipelined microprocessor that prevents the cache from being read when the contents of the cache are invalid May 25, 1995 Issued
Array ( [id] => 3702557 [patent_doc_number] => 05664230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Data processing with adaptable external burst memory access' [patent_app_type] => 1 [patent_app_number] => 8/451645 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3889 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/664/05664230.pdf [firstpage_image] =>[orig_patent_app_number] => 451645 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/451645
Data processing with adaptable external burst memory access May 25, 1995 Issued
Array ( [id] => 3661035 [patent_doc_number] => 05638536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-10 [patent_title] => 'Signal processing apparatus capable of computing replacement data substituted for set data' [patent_app_type] => 1 [patent_app_number] => 8/450725 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2058 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/638/05638536.pdf [firstpage_image] =>[orig_patent_app_number] => 450725 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/450725
Signal processing apparatus capable of computing replacement data substituted for set data May 25, 1995 Issued
Array ( [id] => 3700272 [patent_doc_number] => 05696928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Memory chip architecture for digital storage of prerecorded audio data wherein each of the memory cells are individually addressable' [patent_app_type] => 1 [patent_app_number] => 8/447335 [patent_app_country] => US [patent_app_date] => 1995-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3602 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696928.pdf [firstpage_image] =>[orig_patent_app_number] => 447335 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/447335
Memory chip architecture for digital storage of prerecorded audio data wherein each of the memory cells are individually addressable May 21, 1995 Issued
Array ( [id] => 3537162 [patent_doc_number] => 05504872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'Address translation register control device in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/445554 [patent_app_country] => US [patent_app_date] => 1995-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4874 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504872.pdf [firstpage_image] =>[orig_patent_app_number] => 445554 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/445554
Address translation register control device in a multiprocessor system May 21, 1995 Issued
Array ( [id] => 3659994 [patent_doc_number] => 05630096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order' [patent_app_type] => 1 [patent_app_number] => 8/437975 [patent_app_country] => US [patent_app_date] => 1995-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/630/05630096.pdf [firstpage_image] =>[orig_patent_app_number] => 437975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/437975
Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order May 9, 1995 Issued
Array ( [id] => 3672774 [patent_doc_number] => 05592652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Single-chip microcomputer system having address space allocation hardware for different modes' [patent_app_type] => 1 [patent_app_number] => 8/435565 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9166 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592652.pdf [firstpage_image] =>[orig_patent_app_number] => 435565 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/435565
Single-chip microcomputer system having address space allocation hardware for different modes May 4, 1995 Issued
Array ( [id] => 3634039 [patent_doc_number] => 05615392 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Method and apparatus for consolidated buffer handling for computer device input/output' [patent_app_type] => 1 [patent_app_number] => 8/437125 [patent_app_country] => US [patent_app_date] => 1995-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5180 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/615/05615392.pdf [firstpage_image] =>[orig_patent_app_number] => 437125 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/437125
Method and apparatus for consolidated buffer handling for computer device input/output May 4, 1995 Issued
Array ( [id] => 3675554 [patent_doc_number] => 05625795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Exclusive control unit for a resource shared among computers' [patent_app_type] => 1 [patent_app_number] => 8/433145 [patent_app_country] => US [patent_app_date] => 1995-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 10196 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625795.pdf [firstpage_image] =>[orig_patent_app_number] => 433145 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/433145
Exclusive control unit for a resource shared among computers May 2, 1995 Issued
Array ( [id] => 3830116 [patent_doc_number] => 05812815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Address tenure control for cache management wherein bus master addresses are internally latched in a cache controller' [patent_app_type] => 1 [patent_app_number] => 8/430450 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4724 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/812/05812815.pdf [firstpage_image] =>[orig_patent_app_number] => 430450 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/430450
Address tenure control for cache management wherein bus master addresses are internally latched in a cache controller Apr 27, 1995 Issued
Array ( [id] => 3530306 [patent_doc_number] => 05577218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Memory access control method wherein block access is performed as a sequential access to an address updated by incrementation' [patent_app_type] => 1 [patent_app_number] => 8/428799 [patent_app_country] => US [patent_app_date] => 1995-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1924 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/577/05577218.pdf [firstpage_image] =>[orig_patent_app_number] => 428799 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/428799
Memory access control method wherein block access is performed as a sequential access to an address updated by incrementation Apr 23, 1995 Issued
Array ( [id] => 3677682 [patent_doc_number] => 05668973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Protection system for critical memory information' [patent_app_type] => 1 [patent_app_number] => 8/422435 [patent_app_country] => US [patent_app_date] => 1995-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 8811 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668973.pdf [firstpage_image] =>[orig_patent_app_number] => 422435 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/422435
Protection system for critical memory information Apr 13, 1995 Issued
Array ( [id] => 3440954 [patent_doc_number] => 05463759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/419736 [patent_app_country] => US [patent_app_date] => 1995-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 15484 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463759.pdf [firstpage_image] =>[orig_patent_app_number] => 419736 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/419736
Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system Apr 9, 1995 Issued
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