Search

Olvin Lopez Alvarez

Examiner (ID: 6005, Phone: (571)270-7686 , Office: P/2125 )

Most Active Art Unit
2117
Art Unit(s)
2125, 2121, 2117, 4123
Total Applications
565
Issued Applications
261
Pending Applications
46
Abandoned Applications
274

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19271519 [patent_doc_number] => 20240215226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => Semiconductor Structure and Method of Making the Same [patent_app_type] => utility [patent_app_number] => 17/795121 [patent_app_country] => US [patent_app_date] => 2022-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17795121 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/795121
Semiconductor structure having silicide layer disposed on sidewalls of the bitline May 31, 2022 Issued
Array ( [id] => 18572626 [patent_doc_number] => 20230262964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => MEMORY CELL STRUCTURE, MEMORY ARRAY STRUCTURE, SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/824905 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824905
Memory cell structure, memory array structure, semiconductor structure having a capacitor structure surrounded on the outer side of the word line May 25, 2022 Issued
Array ( [id] => 18743359 [patent_doc_number] => 20230352347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => METHOD FOR MAKING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/752869 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752869
Method for making semiconductor device using a stress memorization technique May 24, 2022 Issued
Array ( [id] => 18306847 [patent_doc_number] => 20230110747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => DISPLAY DEVICE AND METHOD FOR FABRICATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/664853 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664853
Display device including an emission defining layer and method for fabrication thereof May 23, 2022 Issued
Array ( [id] => 18081072 [patent_doc_number] => 20220406684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => IMMERSION DIRECT COOLING MODULES AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/664549 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664549 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664549
Immersion direct cooling modules May 22, 2022 Issued
Array ( [id] => 17840851 [patent_doc_number] => 20220278157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => SOLID-STATE IMAGING DEVICE AND METHOD OF PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 17/749808 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4929 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749808
SOLID-STATE IMAGING DEVICE AND METHOD OF PRODUCING THE SAME May 19, 2022 Pending
Array ( [id] => 19842736 [patent_doc_number] => 12255136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Semiconductor structure and method for manufacturing having the conductive portions isolated from each other by an insulating 2D material [patent_app_type] => utility [patent_app_number] => 17/748111 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 34 [patent_no_of_words] => 6113 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17748111 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/748111
Semiconductor structure and method for manufacturing having the conductive portions isolated from each other by an insulating 2D material May 18, 2022 Issued
Array ( [id] => 19886979 [patent_doc_number] => 12272712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Chip package and method for forming a chip package having first and second stack of dummy metal layers surround the sensing region [patent_app_type] => utility [patent_app_number] => 17/744664 [patent_app_country] => US [patent_app_date] => 2022-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5292 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744664
Chip package and method for forming a chip package having first and second stack of dummy metal layers surround the sensing region May 13, 2022 Issued
Array ( [id] => 18563182 [patent_doc_number] => 11728437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Semiconductor device comprising oxide semiconductor layer containing a c-axis aligned crystal [patent_app_type] => utility [patent_app_number] => 17/741698 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 52 [patent_no_of_words] => 20463 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741698 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741698
Semiconductor device comprising oxide semiconductor layer containing a c-axis aligned crystal May 10, 2022 Issued
Array ( [id] => 18985475 [patent_doc_number] => 11910688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Organic light emitting diode display substrate having band gap layer, manufacturing method thereof, and display device [patent_app_type] => utility [patent_app_number] => 17/742194 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 13482 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17742194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/742194
Organic light emitting diode display substrate having band gap layer, manufacturing method thereof, and display device May 10, 2022 Issued
Array ( [id] => 20118387 [patent_doc_number] => 12368105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Electronic device having a silane coupling agent in an insulating layer [patent_app_type] => utility [patent_app_number] => 17/736067 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 1171 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17736067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/736067
Electronic device having a silane coupling agent in an insulating layer May 2, 2022 Issued
Array ( [id] => 19229758 [patent_doc_number] => 12009402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Method of forming a gate structure in high-k metal gate technology [patent_app_type] => utility [patent_app_number] => 17/735349 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 8110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735349 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735349
Method of forming a gate structure in high-k metal gate technology May 2, 2022 Issued
Array ( [id] => 20361864 [patent_doc_number] => 12477883 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => m-LED, m-LED device, display for augmented reality or lighting applications [patent_app_type] => utility [patent_app_number] => 17/733892 [patent_app_country] => US [patent_app_date] => 2022-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 77 [patent_figures_cnt] => 185 [patent_no_of_words] => 66333 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17733892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/733892
m-LED, m-LED device, display for augmented reality or lighting applications Apr 28, 2022 Issued
Array ( [id] => 18081078 [patent_doc_number] => 20220406690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/731861 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731861
Semiconductor device having a curved part in the printed circuit board Apr 27, 2022 Issued
Array ( [id] => 18308533 [patent_doc_number] => 20230112433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/731180 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731180
Semiconductor structure including conductive layers contacting trench Apr 26, 2022 Issued
Array ( [id] => 18625645 [patent_doc_number] => 11758712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-12 [patent_title] => Manufacturing method of memory device having bit line with stepped profile [patent_app_type] => utility [patent_app_number] => 17/730065 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 6341 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730065
Manufacturing method of memory device having bit line with stepped profile Apr 25, 2022 Issued
Array ( [id] => 19378251 [patent_doc_number] => 12069848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Sense line and cell contact for semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/729450 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6062 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729450 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729450
Sense line and cell contact for semiconductor devices Apr 25, 2022 Issued
Array ( [id] => 18641246 [patent_doc_number] => 11765889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Method to scale dram with self aligned bit line process [patent_app_type] => utility [patent_app_number] => 17/727907 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 4157 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17727907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/727907
Method to scale dram with self aligned bit line process Apr 24, 2022 Issued
Array ( [id] => 17764917 [patent_doc_number] => 20220238530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => METHOD OF FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/659493 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17659493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/659493
Method of forming a semiconductor structure having a gate structure electrically connected to a word line Apr 17, 2022 Issued
Array ( [id] => 17764785 [patent_doc_number] => 20220238398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => Methods of Forming Semiconductor Device Packages [patent_app_type] => utility [patent_app_number] => 17/722935 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10456 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722935 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722935
Method of forming semiconductor device package having testing pads on an upper die Apr 17, 2022 Issued
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