| Application number | Title of the application | Filing Date | Status |
|---|
| 07/890279 | ADDRESS TRANSLATION REGISTER CONTROL DEVICE IN A MULTIPROCESSOR SYSTEM | May 28, 1992 | Abandoned |
Array
(
[id] => 3474234
[patent_doc_number] => 05469555
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system'
[patent_app_type] => 1
[patent_app_number] => 7/889740
[patent_app_country] => US
[patent_app_date] => 1992-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 15500
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/469/05469555.pdf
[firstpage_image] =>[orig_patent_app_number] => 889740
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/889740 | Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system | May 27, 1992 | Issued |
Array
(
[id] => 3497497
[patent_doc_number] => 05426754
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-20
[patent_title] => 'Cross-interrogate method and means for combined scaler and vector processing system'
[patent_app_type] => 1
[patent_app_number] => 7/889022
[patent_app_country] => US
[patent_app_date] => 1992-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 6959
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/426/05426754.pdf
[firstpage_image] =>[orig_patent_app_number] => 889022
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/889022 | Cross-interrogate method and means for combined scaler and vector processing system | May 25, 1992 | Issued |
Array
(
[id] => 3118439
[patent_doc_number] => 05448742
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-05
[patent_title] => 'Method and apparatus for local memory and system bus refreshing with single-port memory controller and rotating arbitration priority'
[patent_app_type] => 1
[patent_app_number] => 7/885430
[patent_app_country] => US
[patent_app_date] => 1992-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 23436
[patent_no_of_claims] => 51
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/448/05448742.pdf
[firstpage_image] =>[orig_patent_app_number] => 885430
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/885430 | Method and apparatus for local memory and system bus refreshing with single-port memory controller and rotating arbitration priority | May 17, 1992 | Issued |
Array
(
[id] => 3437867
[patent_doc_number] => 05404481
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'DMA controller comprising bus switching means for connecting data bus signals with other data bus signals without process or intervention'
[patent_app_type] => 1
[patent_app_number] => 7/883780
[patent_app_country] => US
[patent_app_date] => 1992-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 30
[patent_no_of_words] => 9130
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/404/05404481.pdf
[firstpage_image] =>[orig_patent_app_number] => 883780
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/883780 | DMA controller comprising bus switching means for connecting data bus signals with other data bus signals without process or intervention | May 14, 1992 | Issued |
Array
(
[id] => 3465279
[patent_doc_number] => 05379399
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-03
[patent_title] => 'FIFO memory controller for a digital video communications channel having a detector, comparator, and threshold select logic circuit'
[patent_app_type] => 1
[patent_app_number] => 7/880440
[patent_app_country] => US
[patent_app_date] => 1992-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3278
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/379/05379399.pdf
[firstpage_image] =>[orig_patent_app_number] => 880440
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/880440 | FIFO memory controller for a digital video communications channel having a detector, comparator, and threshold select logic circuit | May 7, 1992 | Issued |
Array
(
[id] => 3120381
[patent_doc_number] => 05418921
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-23
[patent_title] => 'Method and means for fast writing data to LRU cached based DASD arrays under diverse fault tolerant modes'
[patent_app_type] => 1
[patent_app_number] => 7/878810
[patent_app_country] => US
[patent_app_date] => 1992-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 6756
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 405
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/418/05418921.pdf
[firstpage_image] =>[orig_patent_app_number] => 878810
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/878810 | Method and means for fast writing data to LRU cached based DASD arrays under diverse fault tolerant modes | May 4, 1992 | Issued |
Array
(
[id] => 3058724
[patent_doc_number] => 05287481
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-15
[patent_title] => 'Automatic cache flush with readable and writable cache tag memory'
[patent_app_type] => 1
[patent_app_number] => 7/878730
[patent_app_country] => US
[patent_app_date] => 1992-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 26
[patent_no_of_words] => 25058
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/287/05287481.pdf
[firstpage_image] =>[orig_patent_app_number] => 878730
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/878730 | Automatic cache flush with readable and writable cache tag memory | May 3, 1992 | Issued |
Array
(
[id] => 3120400
[patent_doc_number] => 05418922
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-23
[patent_title] => 'History table for set prediction for accessing a set associative cache'
[patent_app_type] => 1
[patent_app_number] => 7/876850
[patent_app_country] => US
[patent_app_date] => 1992-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 13529
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/418/05418922.pdf
[firstpage_image] =>[orig_patent_app_number] => 876850
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/876850 | History table for set prediction for accessing a set associative cache | Apr 29, 1992 | Issued |
| 07/876245 | EXTERNAL INFORMATION STORAGE SYSTEM WITH A SEMICONDUCTOR MEMORY | Apr 29, 1992 | Abandoned |
Array
(
[id] => 3015707
[patent_doc_number] => 05371870
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Stream buffer memory having a multiple-entry address history buffer for detecting sequential reads to initiate prefetching'
[patent_app_type] => 1
[patent_app_number] => 7/874080
[patent_app_country] => US
[patent_app_date] => 1992-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 10723
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/371/05371870.pdf
[firstpage_image] =>[orig_patent_app_number] => 874080
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/874080 | Stream buffer memory having a multiple-entry address history buffer for detecting sequential reads to initiate prefetching | Apr 23, 1992 | Issued |
Array
(
[id] => 3590451
[patent_doc_number] => 05491811
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-13
[patent_title] => 'Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory'
[patent_app_type] => 1
[patent_app_number] => 7/871322
[patent_app_country] => US
[patent_app_date] => 1992-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2708
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/491/05491811.pdf
[firstpage_image] =>[orig_patent_app_number] => 871322
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/871322 | Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory | Apr 19, 1992 | Issued |
Array
(
[id] => 2985023
[patent_doc_number] => 05182802
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-26
[patent_title] => 'Data addressable memory architecture and method of forming a data addressable memory'
[patent_app_type] => 1
[patent_app_number] => 7/864463
[patent_app_country] => US
[patent_app_date] => 1992-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 23
[patent_no_of_words] => 6623
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/182/05182802.pdf
[firstpage_image] =>[orig_patent_app_number] => 864463
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/864463 | Data addressable memory architecture and method of forming a data addressable memory | Apr 5, 1992 | Issued |
Array
(
[id] => 3437853
[patent_doc_number] => 05404480
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Information processor comprising a write buffer circuit containing an address buffer and a data buffer corresponding to each other'
[patent_app_type] => 1
[patent_app_number] => 7/853940
[patent_app_country] => US
[patent_app_date] => 1992-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4234
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/404/05404480.pdf
[firstpage_image] =>[orig_patent_app_number] => 853940
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/853940 | Information processor comprising a write buffer circuit containing an address buffer and a data buffer corresponding to each other | Mar 18, 1992 | Issued |
| 07/851920 | MEMORY ACCESS CONTROL METHOD | Mar 15, 1992 | Abandoned |
| 07/850590 | A MEMORY ACCESS SYSTEM AND METHOD MODIFYING A MEMORY INTERLEAVING SCHEME SO THAT DATA CAN BE READ IN ANY SEQUENCE WITHOUT INSERING WAIT CYCLES | Mar 12, 1992 | Abandoned |
| 07/847300 | PREFETCHING INTO A CACHE TO MINIMIZE MAIN MEMORY ACCESS TIME AND CACHE SIZE IN A COMPUTER SYSTEM | Mar 5, 1992 | Abandoned |
Array
(
[id] => 3437839
[patent_doc_number] => 05404479
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Electronic filing apparatus for filing and retrieving document data in a disk storage medium'
[patent_app_type] => 1
[patent_app_number] => 7/790445
[patent_app_country] => US
[patent_app_date] => 1991-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4138
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 293
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/404/05404479.pdf
[firstpage_image] =>[orig_patent_app_number] => 790445
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/790445 | Electronic filing apparatus for filing and retrieving document data in a disk storage medium | Nov 11, 1991 | Issued |
| 07/767700 | TAG INITIALIZATION IN A CONTROLLER FOR TWO-WAY SET ASSOCIATIVE CACHE | Sep 29, 1991 | Abandoned |
Array
(
[id] => 3058844
[patent_doc_number] => 05335335
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-02
[patent_title] => 'Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed'
[patent_app_type] => 1
[patent_app_number] => 7/753420
[patent_app_country] => US
[patent_app_date] => 1991-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10295
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/335/05335335.pdf
[firstpage_image] =>[orig_patent_app_number] => 753420
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/753420 | Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed | Aug 29, 1991 | Issued |