Omar F. Mojaddedi

Array ( [id] => 16760013 [patent_doc_number] => 10978571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Self-aligned contact with metal-insulator transition materials [patent_app_type] => utility [patent_app_number] => 16/168969 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7003 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168969 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16563587 [patent_doc_number] => 10888941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Power semiconductor module [patent_app_type] => utility [patent_app_number] => 16/168857 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5322 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14221561 [patent_doc_number] => 20190123165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => SEMICONDUCTOR DEVICE AND CMOS TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/169233 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4523 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169233 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15841033 [patent_doc_number] => 20200135799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/169098 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6147 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16536771 [patent_doc_number] => 10879386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Semiconductor device and method of manufacturing a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/168948 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6738 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14446773 [patent_doc_number] => 20190181260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/169040 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14904419 [patent_doc_number] => 20190295975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => SEMICONDUCTOR CHIP, PRINTED CIRCUIT BOARD, MULTI-CHIP PACKAGE INCLUDING THE SEMICONDUCTOR CHIP AND PRINTED CIRCUIT BOARD, AND METHOD OF MANUFACTURING THE MULTI-CHIP PACKAGE [patent_app_type] => utility [patent_app_number] => 16/168653 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15351645 [patent_doc_number] => 20200013714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => NON-VOLATILE MEMORY WITH CAPACITORS USING METAL UNDER SIGNAL LINE OR ABOVE A DEVICE CAPACITOR [patent_app_type] => utility [patent_app_number] => 16/168232 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15807695 [patent_doc_number] => 20200126990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => LDMOS DEVICES, INTEGRATED CIRCUITS INCLUDING LDMOS DEVICES, AND METHODS FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/167842 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15807549 [patent_doc_number] => 20200126917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => SEMICONDUCTOR DEVICES HAVING INTEGRATED OPTICAL COMPONENTS [patent_app_type] => utility [patent_app_number] => 16/168652 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15776041 [patent_doc_number] => 20200119038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => SEMICONDUCTOR DEVICES AND SYSTEMS WITH CHANNEL OPENINGS OR PILLARS EXTENDING THROUGH A TIER STACK, AND METHODS OF FORMATION [patent_app_type] => utility [patent_app_number] => 16/157927 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157927 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15775705 [patent_doc_number] => 20200118870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => HYBRID SIDEWALL BARRIER FACILITATING LOW RESISTANCE INTERCONNECTION [patent_app_type] => utility [patent_app_number] => 16/157897 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16803320 [patent_doc_number] => 10998273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Hybrid integrated circuit architecture [patent_app_type] => utility [patent_app_number] => 16/158212 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6921 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16158212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16760048 [patent_doc_number] => 10978606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Avalanche diode and method of manufacturing an avalanche diode [patent_app_type] => utility [patent_app_number] => 16/157876 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5583 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14382421 [patent_doc_number] => 20190165123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => GATE ETCH BACK WITH REDUCED LOADING EFFECT [patent_app_type] => utility [patent_app_number] => 16/158141 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16158141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15776345 [patent_doc_number] => 20200119190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => VERTICAL TRANSISTOR DEVICES WITH COMPOSITE HIGH-K AND LOW-K SPACERS WITH A CONTROLLED TOP JUNCTION [patent_app_type] => utility [patent_app_number] => 16/157896 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7406 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15922491 [patent_doc_number] => 10658495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Vertical fin type bipolar junction transistor (BJT) device with a self-aligned base contact [patent_app_type] => utility [patent_app_number] => 16/157928 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 7731 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15775713 [patent_doc_number] => 20200118874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => SELF-ALIGNED WRAP-AROUND TRENCH CONTACTS [patent_app_type] => utility [patent_app_number] => 16/157833 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16668570 [patent_doc_number] => 10937828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Fabricating embedded magnetoresistive random access memory device with v-shaped magnetic tunnel junction profile [patent_app_type] => utility [patent_app_number] => 16/157970 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8857 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16636491 [patent_doc_number] => 10914995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => Liquid crystal display panel [patent_app_type] => utility [patent_app_number] => 16/157942 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9672 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157942 [rel_patent_id] =>[rel_patent_doc_number] =>)