Search

Osman M. Alshack

Examiner (ID: 2514, Phone: (571)272-2069 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112
Total Applications
576
Issued Applications
459
Pending Applications
64
Abandoned Applications
69

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14921767 [patent_doc_number] => 10432218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Integrated physical coding sublayer and forward error correction in networking applications [patent_app_type] => utility [patent_app_number] => 16/152514 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5163 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152514 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/152514
Integrated physical coding sublayer and forward error correction in networking applications Oct 4, 2018 Issued
Array ( [id] => 14286973 [patent_doc_number] => 20190140771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => INTEGRATED PHYSICAL CODING SUBLAYER AND FORWARD ERROR CORRECTION IN NETWORKING APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/152479 [patent_app_country] => US [patent_app_date] => 2018-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16152479 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/152479
Integrated physical coding sublayer and forward error correction in networking applications Oct 4, 2018 Issued
Array ( [id] => 14917915 [patent_doc_number] => 10430277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => Multi option rebuilding in a dispersed storage network [patent_app_type] => utility [patent_app_number] => 16/145290 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145290
Multi option rebuilding in a dispersed storage network Sep 27, 2018 Issued
Array ( [id] => 13910905 [patent_doc_number] => 20190044657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => METHOD AND APPARATUS TO MANAGE UNDERSIZED NETWORK PACKETS IN A MEDIA ACCESS CONTROL (MAC) SUBLAYER [patent_app_type] => utility [patent_app_number] => 16/145844 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16145844 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/145844
METHOD AND APPARATUS TO MANAGE UNDERSIZED NETWORK PACKETS IN A MEDIA ACCESS CONTROL (MAC) SUBLAYER Sep 27, 2018 Abandoned
Array ( [id] => 16789876 [patent_doc_number] => 10992319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Code word generating method, erroneous bit determining method, and circuits thereof [patent_app_type] => utility [patent_app_number] => 16/139014 [patent_app_country] => US [patent_app_date] => 2018-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 7863 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 358 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139014 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139014
Code word generating method, erroneous bit determining method, and circuits thereof Sep 21, 2018 Issued
Array ( [id] => 14138985 [patent_doc_number] => 20190103882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => LOW BER HARD-DECISION LDPC DECODER [patent_app_type] => utility [patent_app_number] => 16/137947 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137947 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/137947
Low BER hard-decision LDPC decoder Sep 20, 2018 Issued
Array ( [id] => 14870909 [patent_doc_number] => 20190285696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SEMICONDUCTOR DEVICE AND FAILURE DIAGNOSIS METHOD [patent_app_type] => utility [patent_app_number] => 16/127650 [patent_app_country] => US [patent_app_date] => 2018-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5536 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16127650 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/127650
SEMICONDUCTOR DEVICE AND FAILURE DIAGNOSIS METHOD Sep 10, 2018 Abandoned
Array ( [id] => 14903825 [patent_doc_number] => 20190295678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/124961 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124961 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/124961
SEMICONDUCTOR INTEGRATED CIRCUIT Sep 6, 2018 Abandoned
Array ( [id] => 16759615 [patent_doc_number] => 10978170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Method and system for monitoring information of a memory module in real time [patent_app_type] => utility [patent_app_number] => 16/124379 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9301 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124379 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/124379
Method and system for monitoring information of a memory module in real time Sep 6, 2018 Issued
Array ( [id] => 14811213 [patent_doc_number] => 20190272216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => DATA STORAGE DEVICE AND METHOD OF OPERATING [patent_app_type] => utility [patent_app_number] => 16/124227 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124227 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/124227
Data storage device and method of operating Sep 6, 2018 Issued
Array ( [id] => 16957887 [patent_doc_number] => 11061750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Corrupted track analyzer [patent_app_type] => utility [patent_app_number] => 16/124153 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4648 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/124153
Corrupted track analyzer Sep 5, 2018 Issued
Array ( [id] => 18372380 [patent_doc_number] => 11652566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Forward error correction with outer multi-level code and inner contrast code [patent_app_type] => utility [patent_app_number] => 16/603623 [patent_app_country] => US [patent_app_date] => 2018-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 13234 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603623 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603623
Forward error correction with outer multi-level code and inner contrast code Jul 29, 2018 Issued
Array ( [id] => 15141283 [patent_doc_number] => 10484140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Packet retransmission and memory sharing [patent_app_type] => utility [patent_app_number] => 16/046494 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 12304 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046494 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046494
Packet retransmission and memory sharing Jul 25, 2018 Issued
Array ( [id] => 17031503 [patent_doc_number] => 11093314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Time-sequential data diagnosis device, additional learning method, and recording medium [patent_app_type] => utility [patent_app_number] => 15/734229 [patent_app_country] => US [patent_app_date] => 2018-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6515 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15734229 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/734229
Time-sequential data diagnosis device, additional learning method, and recording medium Jul 22, 2018 Issued
Array ( [id] => 15366055 [patent_doc_number] => 20200018792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => Electronic Interface for Configuring Electronic Communications in Electronic Testing [patent_app_type] => utility [patent_app_number] => 16/034263 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5190 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16034263 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/034263
Electronic Interface for Configuring Electronic Communications in Electronic Testing Jul 11, 2018 Abandoned
Array ( [id] => 16478221 [patent_doc_number] => 10853169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Memory controller, semiconductor memory system including the same, and method of driving the semiconductor memory system [patent_app_type] => utility [patent_app_number] => 16/029083 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7668 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029083 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029083
Memory controller, semiconductor memory system including the same, and method of driving the semiconductor memory system Jul 5, 2018 Issued
Array ( [id] => 17247961 [patent_doc_number] => 20210367706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-25 [patent_title] => DEVICE COMMUNICATION INTERPRETATION BASED ON PROCESS STATE [patent_app_type] => utility [patent_app_number] => 16/606357 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16606357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/606357
DEVICE COMMUNICATION INTERPRETATION BASED ON PROCESS STATE May 20, 2018 Abandoned
Array ( [id] => 17970077 [patent_doc_number] => 11487610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Methods for parity error alert timing interlock and memory devices and systems employing the same [patent_app_type] => utility [patent_app_number] => 15/975703 [patent_app_country] => US [patent_app_date] => 2018-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975703 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/975703
Methods for parity error alert timing interlock and memory devices and systems employing the same May 8, 2018 Issued
Array ( [id] => 17682464 [patent_doc_number] => 11366717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => Systems and methods for error correction [patent_app_type] => utility [patent_app_number] => 16/605620 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8348 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605620 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/605620
Systems and methods for error correction Apr 16, 2018 Issued
Array ( [id] => 16416610 [patent_doc_number] => 10824504 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Common high and low random bit error correction logic [patent_app_type] => utility [patent_app_number] => 15/953805 [patent_app_country] => US [patent_app_date] => 2018-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15953805 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/953805
Common high and low random bit error correction logic Apr 15, 2018 Issued
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