Search

Osman M. Alshack

Examiner (ID: 5354, Phone: (571)272-2069 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112
Total Applications
553
Issued Applications
447
Pending Applications
61
Abandoned Applications
69

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10493790 [patent_doc_number] => 20150378812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'System and Method for Error Recovery in an Asynchronous FIFO' [patent_app_type] => utility [patent_app_number] => 14/316435 [patent_app_country] => US [patent_app_date] => 2014-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14316435 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/316435
System and Method for Error Recovery in an Asynchronous FIFO Jun 25, 2014 Abandoned
Array ( [id] => 12819943 [patent_doc_number] => 20180165153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => Integrated Circuit and Programmable Device [patent_app_type] => utility [patent_app_number] => 15/317230 [patent_app_country] => US [patent_app_date] => 2014-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15317230 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/317230
Integrated circuit and programmable device Jun 17, 2014 Issued
Array ( [id] => 11200914 [patent_doc_number] => 09431132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Data managing method, memory control circuit unit and memory storage apparatus' [patent_app_type] => utility [patent_app_number] => 14/307509 [patent_app_country] => US [patent_app_date] => 2014-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6157 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 442 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14307509 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/307509
Data managing method, memory control circuit unit and memory storage apparatus Jun 17, 2014 Issued
Array ( [id] => 9814584 [patent_doc_number] => 20150026529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-22 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF EVALUATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/306274 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9872 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14306274 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/306274
SEMICONDUCTOR DEVICE AND METHOD OF EVALUATING SEMICONDUCTOR DEVICE Jun 16, 2014 Abandoned
Array ( [id] => 10969780 [patent_doc_number] => 20140372813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'METHOD FOR VERIFYING BAD PATTERN IN TIME SERIES SENSING DATA AND APPARATUS THEREOF' [patent_app_type] => utility [patent_app_number] => 14/306967 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9223 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14306967 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/306967
Method for verifying bad pattern in time series sensing data and apparatus thereof Jun 16, 2014 Issued
Array ( [id] => 11228019 [patent_doc_number] => 09455748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-27 [patent_title] => 'Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal' [patent_app_type] => utility [patent_app_number] => 14/305974 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 76 [patent_figures_cnt] => 120 [patent_no_of_words] => 27995 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14305974 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/305974
Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal Jun 15, 2014 Issued
Array ( [id] => 10969802 [patent_doc_number] => 20140372835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'COMPUTING SYSTEM WITH DECODING ADJUSTMENT MECHANISM AND METHOD OF OPERATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/305646 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 16963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14305646 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/305646
Computing system with decoding adjustment mechanism and method of operation thereof Jun 15, 2014 Issued
Array ( [id] => 10314229 [patent_doc_number] => 20150199232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-16 [patent_title] => 'IMPLEMENTING ECC CONTROL FOR ENHANCED ENDURANCE AND DATA RETENTION OF FLASH MEMORIES' [patent_app_type] => utility [patent_app_number] => 14/305045 [patent_app_country] => US [patent_app_date] => 2014-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2816 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14305045 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/305045
Implementing ECC control for enhanced endurance and data retention of flash memories Jun 15, 2014 Issued
Array ( [id] => 10478246 [patent_doc_number] => 20150363263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'ECC Encoder Using Partial-Parity Feedback' [patent_app_type] => utility [patent_app_number] => 14/303393 [patent_app_country] => US [patent_app_date] => 2014-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5359 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14303393 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/303393
ECC Encoder Using Partial-Parity Feedback Jun 11, 2014 Abandoned
Array ( [id] => 9758876 [patent_doc_number] => 20140289578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'SCAN CIRCUIT HAVING FIRST SCAN FLIP-FLOPS AND SECOND SCAN FLIP-FLOPS' [patent_app_type] => utility [patent_app_number] => 14/298061 [patent_app_country] => US [patent_app_date] => 2014-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7951 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14298061 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/298061
SCAN CIRCUIT HAVING FIRST SCAN FLIP-FLOPS AND SECOND SCAN FLIP-FLOPS Jun 5, 2014 Abandoned
Array ( [id] => 11247122 [patent_doc_number] => 09473174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Interleaving for layer-aware forward error correction' [patent_app_type] => utility [patent_app_number] => 14/277925 [patent_app_country] => US [patent_app_date] => 2014-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 13466 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14277925 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/277925
Interleaving for layer-aware forward error correction May 14, 2014 Issued
Array ( [id] => 10157547 [patent_doc_number] => 09189325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Memory system and operation method thereof' [patent_app_type] => utility [patent_app_number] => 14/273757 [patent_app_country] => US [patent_app_date] => 2014-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11061 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14273757 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/273757
Memory system and operation method thereof May 8, 2014 Issued
Array ( [id] => 10137561 [patent_doc_number] => 09170881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Solid state device coding architecture for chipkill and endurance improvement' [patent_app_type] => utility [patent_app_number] => 14/266702 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6870 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14266702 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/266702
Solid state device coding architecture for chipkill and endurance improvement Apr 29, 2014 Issued
Array ( [id] => 9618298 [patent_doc_number] => 20140208154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'STORING DATA IN A DISPERSED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 14/223406 [patent_app_country] => US [patent_app_date] => 2014-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 29763 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223406 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/223406
Storing data in a dispersed storage network Mar 23, 2014 Issued
Array ( [id] => 9604885 [patent_doc_number] => 20140201567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'ENCODING DATA UTILIZING A ZERO INFORMATION GAIN FUNCTION' [patent_app_type] => utility [patent_app_number] => 14/217662 [patent_app_country] => US [patent_app_date] => 2014-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 21356 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217662 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/217662
Encoding data utilizing a zero information gain function Mar 17, 2014 Issued
Array ( [id] => 9746061 [patent_doc_number] => 20140281780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'ERROR DETECTION AND RECOVERY OF TRANSMISSION DATA IN COMPUTING SYSTEMS AND ENVIRONMENTS' [patent_app_type] => utility [patent_app_number] => 14/211043 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6584 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14211043 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/211043
ERROR DETECTION AND RECOVERY OF TRANSMISSION DATA IN COMPUTING SYSTEMS AND ENVIRONMENTS Mar 13, 2014 Abandoned
Array ( [id] => 10557631 [patent_doc_number] => 09281840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'System and method for multi standard programmable LDPC decoder' [patent_app_type] => utility [patent_app_number] => 14/211616 [patent_app_country] => US [patent_app_date] => 2014-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5804 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 515 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14211616 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/211616
System and method for multi standard programmable LDPC decoder Mar 13, 2014 Issued
Array ( [id] => 11484088 [patent_doc_number] => 09590656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'System and method for higher quality log likelihood ratios in LDPC decoding' [patent_app_type] => utility [patent_app_number] => 14/210067 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8943 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14210067 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/210067
System and method for higher quality log likelihood ratios in LDPC decoding Mar 12, 2014 Issued
Array ( [id] => 10376594 [patent_doc_number] => 20150261601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'Network Synchronization for Master and Slave Devices' [patent_app_type] => utility [patent_app_number] => 14/207265 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14207265 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/207265
Network synchronization for master and slave devices Mar 11, 2014 Issued
Array ( [id] => 9746052 [patent_doc_number] => 20140281771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'METHOD AND DEVICE FOR OPTIMIZING LOG LIKELIHOOD RATIO (LLR) USED FOR NONVOLATILE MEMORY DEVICE AND FOR CORRECTING ERRORS IN NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/205482 [patent_app_country] => US [patent_app_date] => 2014-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 12254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205482 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/205482
Method and device for optimizing log likelihood ratio (LLR) used for nonvolatile memory device and for correcting errors in nonvolatile memory device Mar 11, 2014 Issued
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