Search

Otilia Gabor

Examiner (ID: 2881)

Most Active Art Unit
2878
Art Unit(s)
2878, 2884
Total Applications
620
Issued Applications
492
Pending Applications
59
Abandoned Applications
69

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6933878 [patent_doc_number] => 20010055222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell' [patent_app_type] => new [patent_app_number] => 09/894134 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11734 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 534 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20010055222.pdf [firstpage_image] =>[orig_patent_app_number] => 09894134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894134
Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Jun 28, 2001 Issued
Array ( [id] => 4418638 [patent_doc_number] => 06310818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Semiconductor memory device and method of changing output data of the same' [patent_app_type] => 1 [patent_app_number] => 9/817221 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9330 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310818.pdf [firstpage_image] =>[orig_patent_app_number] => 817221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817221
Semiconductor memory device and method of changing output data of the same Mar 26, 2001 Issued
Array ( [id] => 4418529 [patent_doc_number] => 06310807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Semiconductor integrated circuit device including tester circuit for defective memory cell replacement' [patent_app_type] => 1 [patent_app_number] => 9/813917 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 33 [patent_no_of_words] => 15703 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310807.pdf [firstpage_image] =>[orig_patent_app_number] => 813917 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/813917
Semiconductor integrated circuit device including tester circuit for defective memory cell replacement Mar 21, 2001 Issued
Array ( [id] => 7639157 [patent_doc_number] => 06396760 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Memory having a redundancy scheme to allow one fuse to blow per faulty memory column' [patent_app_type] => B1 [patent_app_number] => 09/810817 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4793 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396760.pdf [firstpage_image] =>[orig_patent_app_number] => 09810817 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810817
Memory having a redundancy scheme to allow one fuse to blow per faulty memory column Mar 15, 2001 Issued
Array ( [id] => 1437700 [patent_doc_number] => 06356495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-03-12 [patent_title] => 'Memory array architecture, method of operating a dynamic random access memory, and method of manufacturing a dynamic random access memory' [patent_app_type] => B2 [patent_app_number] => 09/804617 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3631 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356495.pdf [firstpage_image] =>[orig_patent_app_number] => 09804617 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/804617
Memory array architecture, method of operating a dynamic random access memory, and method of manufacturing a dynamic random access memory Mar 11, 2001 Issued
Array ( [id] => 1555109 [patent_doc_number] => 06400612 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Memory based on a four-transistor storage cell' [patent_app_type] => B1 [patent_app_number] => 09/802715 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2694 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400612.pdf [firstpage_image] =>[orig_patent_app_number] => 09802715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802715
Memory based on a four-transistor storage cell Mar 7, 2001 Issued
Array ( [id] => 1480094 [patent_doc_number] => 06344998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-05 [patent_title] => 'Electrically alterable non-volatile memory with N-Bits per cell' [patent_app_type] => B2 [patent_app_number] => 09/794042 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7204 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 835 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344998.pdf [firstpage_image] =>[orig_patent_app_number] => 09794042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794042
Electrically alterable non-volatile memory with N-Bits per cell Feb 27, 2001 Issued
Array ( [id] => 6876324 [patent_doc_number] => 20010006477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-05 [patent_title] => 'Electrically alterable non-volatile memory with n-bits per cell' [patent_app_type] => new-utility [patent_app_number] => 09/794032 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10514 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20010006477.pdf [firstpage_image] =>[orig_patent_app_number] => 09794032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794032
Electrically alterable non-volatile memory with n-bits per cell Feb 27, 2001 Issued
Array ( [id] => 6887495 [patent_doc_number] => 20010008489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-19 [patent_title] => 'Electrically alterable non-volatile memory with n-bits per cell' [patent_app_type] => new-utility [patent_app_number] => 09/794031 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10485 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20010008489.pdf [firstpage_image] =>[orig_patent_app_number] => 09794031 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794031
Electrically alterable non-volatile memory with n-bits per cell Feb 27, 2001 Issued
Array ( [id] => 1567617 [patent_doc_number] => 06339545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-01-15 [patent_title] => 'Electrically alterable non-volatile memory with n-bits per cell' [patent_app_type] => B2 [patent_app_number] => 09/794043 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7207 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 767 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339545.pdf [firstpage_image] =>[orig_patent_app_number] => 09794043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794043
Electrically alterable non-volatile memory with n-bits per cell Feb 27, 2001 Issued
Array ( [id] => 4419328 [patent_doc_number] => 06301172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Gate voltage testkey for isolation transistor' [patent_app_type] => 1 [patent_app_number] => 9/794513 [patent_app_country] => US [patent_app_date] => 2001-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7352 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301172.pdf [firstpage_image] =>[orig_patent_app_number] => 794513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/794513
Gate voltage testkey for isolation transistor Feb 26, 2001 Issued
Array ( [id] => 1433805 [patent_doc_number] => 06341095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Apparatus for increasing pulldown rate of a bitline in a memory device during a read operation' [patent_app_type] => B1 [patent_app_number] => 09/788819 [patent_app_country] => US [patent_app_date] => 2001-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341095.pdf [firstpage_image] =>[orig_patent_app_number] => 09788819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788819
Apparatus for increasing pulldown rate of a bitline in a memory device during a read operation Feb 20, 2001 Issued
Array ( [id] => 1555939 [patent_doc_number] => 06349058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Electronic circuit and method for storing configuration and calibration information in a non-volatile memory array' [patent_app_type] => B1 [patent_app_number] => 09/785121 [patent_app_country] => US [patent_app_date] => 2001-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2615 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349058.pdf [firstpage_image] =>[orig_patent_app_number] => 09785121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785121
Electronic circuit and method for storing configuration and calibration information in a non-volatile memory array Feb 15, 2001 Issued
Array ( [id] => 6897995 [patent_doc_number] => 20010046160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Memory device' [patent_app_type] => new [patent_app_number] => 09/750040 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 11248 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046160.pdf [firstpage_image] =>[orig_patent_app_number] => 09750040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750040
Memory device Dec 28, 2000 Issued
Array ( [id] => 4339499 [patent_doc_number] => 06330203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Test mode for verification of on-chip generated row addresses' [patent_app_type] => 1 [patent_app_number] => 9/747233 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2922 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330203.pdf [firstpage_image] =>[orig_patent_app_number] => 747233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/747233
Test mode for verification of on-chip generated row addresses Dec 25, 2000 Issued
Array ( [id] => 6901165 [patent_doc_number] => 20010022748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Virtual channel synchronous dynamic random access memory' [patent_app_type] => new [patent_app_number] => 09/741419 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3381 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20010022748.pdf [firstpage_image] =>[orig_patent_app_number] => 09741419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741419
Virtual channel synchronous dynamic random access memory Dec 20, 2000 Issued
Array ( [id] => 6921112 [patent_doc_number] => 20010028597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Semiconductor memory of the dynamic random access type (DRAM) and method for actuating a memory cell' [patent_app_type] => new [patent_app_number] => 09/739543 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1856 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20010028597.pdf [firstpage_image] =>[orig_patent_app_number] => 09739543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739543
Semiconductor memory of the dynamic random access type (DRAM) and method for actuating a memory cell Dec 14, 2000 Issued
Array ( [id] => 4286778 [patent_doc_number] => 06324102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Radiation tolerant flash FPGA' [patent_app_type] => 1 [patent_app_number] => 9/737643 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2677 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324102.pdf [firstpage_image] =>[orig_patent_app_number] => 737643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/737643
Radiation tolerant flash FPGA Dec 13, 2000 Issued
Array ( [id] => 1525617 [patent_doc_number] => 06353554 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell' [patent_app_type] => B1 [patent_app_number] => 09/733937 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11603 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 845 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353554.pdf [firstpage_image] =>[orig_patent_app_number] => 09733937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733937
Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Dec 11, 2000 Issued
Array ( [id] => 4384310 [patent_doc_number] => 06288946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method of erasing a flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/722313 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1793 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288946.pdf [firstpage_image] =>[orig_patent_app_number] => 722313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722313
Method of erasing a flash memory device Nov 27, 2000 Issued
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